Warm Reset Flow; Sleep Mode Sequence Of Operation; Signals And Constraints For The Sleep Mode Sequence; Effect On Iprs After Warm Reset - Compaq 21264 Hardware Reference Manual

Figure 7–3 Sleep Mode Sequence of Operation
state
RUN
SLEEP IPR
Wake-up interrupt
SromOE_L
ClkFwdRst_H
TestStat_H
internal ClkFwdRst
external Clks
Table 7–7 describes each signal and constraint for the sleep mode sequence.
Table 7–7 Signals and Constraints for the Sleep Mode Sequence
Signal Name Description
ClkFwdRst_H Signal asserted by the system to
initialize and reset clock forwarding
interfaces
Forwarded clocks Bit clocks forwarded to/from the
21264/EV67
System interrupt Asynchronous interrupt which
causes the 21264/EV67 to exit sleep
mode

7.4 Warm Reset Flow

The warm reset sequence of operation is triggered by the assertion of the Reset_L sig-
nal line. The reset state machine is initially in RUN state. The 21264/EV67 then, by
default, ramps down the PLL (similar to the sleep flow sequence) and the reset state
machine ends up in the WAIT_RESET state.
Note the effects of entry into that state on the IPRs listed in Table 7–8
Table 7–8 Effect on IPRs After Warm Reset
IPR
PAL_BASE
I_CTL
PCTX[FPE]
WRITE_MANY Cleared (That is, the WRITE_MANY chain is initialized and the Bcache is
Alpha 21264/EV67 Hardware Reference Manual
DOWN1 DOWN2 DOWN3 WAIT_INTR
Effects After Warm Reset
Cleared
Cleared
Set
turned off.)
internal clks
b
RAMP1 RAMP2 WAIT_ClkFwdRst0 WAIT_BiSI
a
c
no min
A
Constraint
ClkFwdRst_H must be asserted by the system
when entering sleep mode. The system deasserts
ClkFwdRst_H no sooner than one FrameClk_H
cycle after sourcing an interrupt to the 21264/
EV67.
Clocks stop running under ClkFwdRst_H.
—
Initialization and Configuration
Warm Reset Flow
f
WAIT_ClkFwdRst1 RUN
e
no min
d
FM-06487A.AI4
.
7–11