Ev67 Reset State Machine State Diagram; Ev67 Reset State Machine State Descriptions - Compaq 21264 Hardware Reference Manual

Figure 7–5 21264/EV67 Reset State Machine State Diagram
PLL Ramp Up
DCOK_H
asserted
WAIT_
SETTLE
[16,32]
Reset_L
asserted
Enabled
COLD
Interrupt
Reset_L
asserted
WAIT_
INTERRUPT
Counter
finished &
Sleep Mode
DOWN3
[16,32]
Table 7–11 21264/EV67 Reset State Machine State Descriptions
State Name Description
COLD Chip cold. Transitioned to WAIT_SETTLE with assertion of Reset_L, PLL_VDD, and
VDD.
WAIT_SETTLE PLL_VDD asserted; PLL at minimum frequency.
WAIT_NOMINAL Triggered by assertion of DCOK_H. PLL achieves a lock at X
16 and 32, respectively.
RAMP1 Triggered by Reset_L deassertion; X
tively, increasing the internal GCLK frequency. An internal duration counter is initial-
ized to count 4108 GCLK cycles.
Alpha 21264/EV67 Hardware Reference Manual
Reset_L
RAMP1
deasserted
[2,4]
WAIT_
NOMINAL
[16,32]
Reset_L
deasserted
WAIT_
RESET
Numbers in "[,]" are
Xdiv and Zdiv divisors,
respectively
Counter
finished &
not Sleep Mode
PLL Ramp Down
Counter
finished
DOWN2
[2,4]
Counter
finished
RAMP2
[1,2]
Counter
ClkFwdRst_H
finished
deasserted
WAIT_
BiST
FAULT_
BiST
RESET
finished
ClkFwdRst_H
asserted
*No BiST/BiSI
on recovery from Fault
Reset
Counter
finished
DOWN1
Sleep Mode
[1,2]
or Reset_L
asserted
and Z divisors are changed to 2 and 4, respec-
div div
Initialization and Configuration
Reset State Machine
Counter
finished
WAIT_ClkFwd
Rst0
Out of
Sleep
Mode
Out of
FAULT_
WAIT_
RESET*
BiSI
BiSI
finished
WAIT_ClkFwd
Rst1
ClkFwdRst_H
deasserted
RUN
LKG-10982A-98WF
and Z divisors equal
div div
7–17