Effect On Iprs After Transition Through Sleep Mode - Compaq 21264 Hardware Reference Manual

Energy Star Certification and Sleep Mode Flow
After the PLL has finished ramping down, the reset state machine enters the
WAIT_INTERRUPT state. Note the effects of the entry into that state on the IPRs
listed in Table 7–6.
Table 7–6 Effect on IPRs After Transition Through Sleep Mode
IPR
PAL_BASE
I_CTL
PCTX[FPE]
WRITE_MANY Cleared (That is, the WRITE_MANY chain is initialized and the Bcache is
Note that Interrupt enables are maintained during sleep mode, enabling the 21264/
EV67 to wake up. The 21264/EV67 waits for either an unmasked clock interrupt or an
unmasked device interrupt from the system.
When an enabled interrupt occurs, the PLL ramps back to full frequency. Subsequent to
that, the 21264/EV67 performs a built-in self-initialization (BiSI), a shortened built-in
self-test, which initializes the internal arrayed structures. The SROM is not reloaded.
Instead, the 21264/EV67 begins fetching code from the system at address PAL_BASE
+ 0x780.
Figure 7–3 shows the sleep mode sequence of operations. In Figure 7–3, note the fol-
lowing constraint and informational symbols:
Constraints:
A Min = 1 FrameClk_x cycle
Informational symbols:
a Approximately 525 GCLK cycles for external framing clock to be sampled and captured
b Next FrameClk_x rising edge
c 1 FrameClk_x cycle
d 3 FrameClk_x cycles
e Approximately 264 GCLK cycles to prevent first command from appearing too early
f Approximately 8192 GCLK cycles for BiSI
g 16 GCLK cycles
Initialization and Configuration
7–10
Effects After Transition Through Sleep Mode
Maintained (not reset)
Bit value = 3 (both Icaches are enabled)
Set
turned off.)
Alpha 21264/EV67 Hardware Reference Manual