Ibox Status Register; Ibox Status Register Fields Description - Compaq 21264 Hardware Reference Manual

Figure 5–23 Ibox Status Register
63
MIS
TRP
LS0
TRAP TYPE[3:0]
ICM
OVR[2:0]
PAR
Table 5–12 describes the Ibox status register fields.
Table 5–12 Ibox Status Register Fields Description
Name Extent
Reserved [63:41]
MIS [40]
TRP [39]
LS0 [38]
Alpha 21264/EV67 Hardware Reference Manual
41 40 39 38 37
Type Description
RO Reserved for Compaq.
RO ProfileMe Mispredict Trap.
If the I_STAT[TRP] bit is set, this bit indicates that the profiled instruc-
tion caused a mispredict trap. JSR/JMP/RET/COR or HW_JSR/
HW_JMP/HW_RET/HW_COR mispredicts do not set this bit but can be
recognized by the presence of one of these instructions at the PMPC loca-
tion with the I_STAT[TRP] bit set. This identification is exact in all cases
except error condition traps. Hardware corrected Icache parity or Dcache
ECC errors, and machine check traps can occur on any instruction in the
pipeline.
RO ProfileMe Trap.
This bit indicates that the profiled instruction caused a trap. The trap type
field, PMPC register, and instruction at the PMPC location are needed to
distinguish all trap types.
RO ProfileMe Load-Store Order Trap.
If the profiled instruction caused a replay trap, this bit indicates that the
precise trap cause was an Mbox load-store order replay trap.
If clear, this bit indicates that the replay trap was any one of the follow-
ing:
Mbox load-load order
Mbox load queue full
Mbox store queue full
Mbox wrong size trap (such as, STL
Mbox Bcache alias (2 physical addresses map to same Bcache line)
Mbox Dcache alias (2 physical addresses map to same Dcache line)
Icache parity error
Dcache ECC error
34 33 32 30 29 28
Internal Processor Registers
Ibox IPRs
LK99-0031A
LDQ)
5–19
0