System Probes And Sysdc Commands; Bcache Port; Bcache Port Pins; Rules For System Control Of Cache Status Update Order - Compaq EV68A Hardware Reference Manual

Bcache Port

4.7.10.2 System Probes and SysDc Commands

Ordering of cache transactions at the system serialization point must be reflected in the
21264/EV68A cache system. Table 4–34 shows the rules that a system must follow to
control the order of cache status update within the 21264/EV68A cache structures
(including the VAF) at the 21264/EV68A pins.
Table 4–34 Rules for System Control of Cache Status Update Order
First Second
Probe Probe
Probe SysDc MAF
Probe SysDc VAF
SysDc MAF Probe
SysDc MAF SysDc MAF
SysDc MAF SysDc VAF
SysDc VAF Probe
SysDc VAF SysDc MAF
SysDc VAF SysDc VAF
4.8 Bcache Port
The 21264/EV68A supports a second-level cache (Bcache) with 64-byte blocks. The
Bcache size can be 1MB, 2MB, 4MB, 8MB, or 16MB. The Bcache port has a 144-bit
data bus that is used for data transfers between the 21264/EV68A and the Bcache. All
Bcache control and address signal lines are clocked synchronously on Bcache clock cycle
boundaries.
Cache and External Interfaces
4–42
Rule
To control the sequence of cache status updates between probes, systems
can present the probes in order to the 21264/EV68A, and the 21264/
EV68A will update the appropriate cache state (including the VAF) in
order.
To ensure that a probe updates the internal cache status before a SysDc
MAF transaction (including fills and ChangeToDirtySuccess commands),
systems must wait for the probe response before presenting the SysDc
MAF command to the 21264/EV68A. To ensure that a probe updates a
VAF entry before a SysDc VAF (release buffer), systems must wait for the
probe response.
Same as Probe/SysDc MAF, above.
To ensure that a SysDc MAF command updates the 21264/EV68A cache
system before a probe to the same address, systems must deliver the D1
(the second QW of data delivered to the 21264/EV68A) before or in the
same cycle as the A3 of the probe (the last cycle of the 4-cycle probe com-
mand). This rule also applies to ChangeToDirtySuccess commands that
have a virtual D0 and D1 transaction.
SysDc MAF transactions can be ordered into the 21264/EV68A by order-
ing them appropriately at the 21264/EV68A interface.
SysDc MAF transactions and SysDc VAF transactions cannot interact
within the 21264/EV68A because the 21264/EV68A does not generate
MAF transactions to the same address as existing VAF transactions.
To ensure that a SysDc VAF invalidates a VAF entry before a probe to the
same address, the SysDc VAF command must precede the first cycle of the
4-cycle probe command.
SysDc MAF transactions and SysDc VAF transactions cannot interact
within the 21264/EV68A because the 21264/EV68A does not generate
MAF transactions to the same address as existing VAF transactions.
SysDc VAF transactions can be ordered into the 21264/EV68A by order-
ing them appropriately at the 21264/EV68A interface.
21264/EV68A Hardware Reference Manual