Compaq 21264 Hardware Reference Manual page 177

Table 5–24 Cbox WRITE_ONCE Chain Order (Continued)
Cbox WRITE_ONCE Chain
DUP_TAG_ENABLE
SKEWED_FILL_MODE
BC_RDVICTIM
SKEWED_FILL_MODE
BC_RDVICTIM
BC_CLEAN_VICTIM
DUP_TAG_MODE
SKEWED_FILL_MODE
ENABLE_PROBE_CHECK
SPEC_READ_ENABLE[0]
SKEWED_FILL_MODE
SKEWED_FILL_MODE
MBOX_BC_PRB_STALL
BC_LAT_DATA_PATTERN[0:31]
BC_LAT_TAG_PATTERN[0:23]
BC_RDVICTIM
ENABLE_STC_COMMAND[0]
BC_LATE_WRITE_NUM[0:2]
BC_CPU_LATE_WRITE_NUM[0:1]
BC_BURST_MODE_ENABLE[0]
BC_PENTIUM_MODE[0]
SKEWED_FILL_MODE
BC_FRM_CLK[0]
BC_CLK_DELAY[0:1]
BC_DDMR_ENABLE[0]
BC_DDMF_ENABLE[0]
BC_LATE_WRITE_UPPER[0]
BC_TAG_DDM_FALL_EN[0]
Alpha 21264/EV67 Hardware Reference Manual
Description
Duplicate CSR.
Duplicate CSR.
Duplicate CSR.
Duplicate CSR.
Duplicate CSR.
Duplicate CSR.
Duplicate CSR.
Duplicate CSR.
Enable error checking during probe processing.
Enable speculative references to the system port.
Duplicate CSR.
Duplicate CSR.
Must be asserted when BC_RATIO = 4.0X, 5.0X, 6.0X, 7.0X, or
8.0X.
Bcache data latency pattern.
Bcache tag latency pattern.
Duplicate CSR.
Enable STx_C instructions to the pins.
Number of Bcache clocks to delay the data for Bcache write com-
mands.
Number of GCLK cycles to delay the Bcache clock/data from
index.
Burst mode enable signal.
Enable Pentium mode RAM behavior.
Duplicate CSR.
Force all Bcache transactions to start on rising edges of the A phase
of a GCLK.
Delay of Bcache clock for 0,0,1,2 GCLK phases.
Enables the rising edge of the Bcache forwarded clock (always
enabled).
Enable the falling edge of the Bcache forwarded clock. (always
enabled).
Asserted when (BC_LATE_WRITE_NUM > 3) or
((BC_LATE_WRITE_NUM = 3) and
(BC_CPU_LATE_WRITE_NUM > 1)).
Enables the update of the 21264/EV67 Bcache tag outputs based on
the falling edge of the forwarded clock.
Cbox CSRs and IPRs
Internal Processor Registers
5–35