Compaq 21264 Hardware Reference Manual page 348

Dcache
,
described 2–12
duplicate tag parity errors
,
duplicate tags with 4–13
error case summary for
fill from Bcache error
fill from memory errors
,
initialized by BiST 7–12
,
pipelined 2–16
single-bit correctable ECC error
,
store second error 8–4
,
tag parity errors 8–2
,
victim extracts 8–4
Dcache data single-bit correctable ECC errors
Dcache tag, initialized by BiST
,
DCOK_H signal pin 3–4
,
power-on reset flow
DCVIC_THRESHOLD Cbox CSR, defined
,
DFAULT fault 6–13
Differential 21264/EV67 clocks
Differential reference clocks
,
Dirty cache block state 4–10
Dirty/Shared cache block state
,
Do not care convention xxi
,
Double-bit fill errors 8–9
DOWN1 reset machine state
DOWN2 reset machine state
DOWN3 reset machine state
Dstream translation buffer
See also DTB
DSTREAM_BC_DBL error status in C_STAT
5–41
DSTREAM_BC_ERR error status in C_STAT
5–41
DSTREAM_DC_ERR error status in C_STAT
5–41
DSTREAM_MEM_DBL error status in C_STAT
5–41
DSTREAM_MEM_ERR error status in C_STAT
5–41
DTAG. See Duplicate Dcache tag array
DTB entries, writing multiple in same PAL flow
D–19
,
DTB fill 6–14
DTB, pipeline abort delay with
DTB_ALTMODE alternate processor mode register
5–26
at power-on reset state
Index–4
,
8–4
,
8–9
,
8–6
,
8–7
,
8–3
,
8–3
,
7–12
7–1
,
5–34
,
7–19
,
7–19
,
4–10
,
7–18
,
7–19
,
7–19
,
2–13
,
,
,
,
,
,
,
2–16
,
,
7–15
DTB_ASN0 address space number register 0
at power-on reset state
DTB_ASN0 address space number registers 0
DTB_ASN1 address space number register 1
at power-on reset state
DTB_IA invalidate-all process register
at power-on reset state
DTB_IAP invalidate-all (ASM=0) process register
5–27
at power-on reset state
DTB_IS0 invalidate single (array 0) register
at power-on reset state
DTB_IS1 invalidate single (array 1) register
at power-on reset state
DTB_PTE0 array write 0 register
at power-on reset state
,
MTPR to D–12
DTB_PTE0 array write register 0
DTB_PTE1 array write 1 register
at power-on reset state
,
MTPR to D–12
DTB_TAG0 array write 0 register
at power-on reset state
,
MTPR to D–12
DTB_TAG1 array write 1 register
at power-on reset state
,
MTPR to D–12
DTBM_DOUBLE_3 fault
DTBM_DOUBLE_4 fault
,
DTBM_SINGLE fault
Dual-data rate SSRAM pin assignments
DUP_TAG_ENABLE Cbox CSR, defined
Duplicate Dcache tag array
Duplicate Dcache, initialized by BiST
Duplicate tag array, Cbox copy. See CTAG
Duplicate tag stores, Bcache
E
Ebox
cycle counter control register CC_CTL
cycle counter register CC
,
described 2–8
executed in pipeline
internal processor registers
,
slotting 2–18
,
subclusters 2–18
virtual address control register VA_CTL
virtual address format register VA_FORM
virtual address register
ECB instruction, external interface reference
Alpha 21264/EV67 Hardware Reference Manual
,
7–16
,
5–28
,
5–28
,
7–16
,
5–27
,
7–15
,
7–15
,
5–27
,
7–16
,
5–27
,
7–16
,
7–15
,
5–26
,
5–26
,
7–15
,
5–25
,
7–15
,
5–25
,
7–15
,
6–13
,
6–13
6–13
,
E–3
,
5–34
,
2–11
,
7–12
,
4–7
,
5–3
,
5–3
,
2–16
,
5–1
,
5–4
,
5–5
,
5–4
,
4–5
,