Compaq 21264 Hardware Reference Manual page 162

Compaq microprocessor reference manual
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Ibox IPRs
Table 5–12 Ibox Status Register Fields Description (Continued)
Name
Extent
TRAP
[37:34]
TYPE[3:0]
ICM
[33]
OVR[2:0]
[32:30]
PAR
[29]
Reserved
[28:0]
Internal Processor Registers
5–20
Type
Description
RO
ProfileMe Trap Types.
If the profiled instruction caused a trap (indicated by I_STAT[TRP]), this
field indicates the trap type as listed here:
Value
Trap Type
0
Replay
1
Invalid (unused)
2
DTB Double miss (3 level page tables)
3
DTB Double miss (4 level page tables)
4
Floating point disabled
5
Unaligned Load/Store
6
DTB Single miss
7
Dstream Fault
8
OPCDEC
9
Invalid (use PMPC, described below)
10
Machine Check
11
Invalid (use PMPC, described below)
12
Arithmetic
13
Invalid (use PMPC, described below)
14
MT_FPCR
15
Reset
Traps due to ITB miss, Istream access violation, or interrupts are not
reported in the trap type field because they do not cause pipeline aborts.
Instead, these traps cause pipeline redirection and can be distinguished by
examining the PMPC value for the presence of the corresponding PAL-
code entry offset addresses indicated below. In these cases, the ProfileMe
interrupt will normally be delivered when exiting the trap PALcode flow
and the EXC_ADDR register will contain the original PC that encoun-
tered the redirect trap.
PMPC[14:0]
0581
0481
0681
RO
ProfileMe Icache Miss.
This bit indicates that the profiled instruction was contained in an aligned
4-instruction Icache fetch block that requested a new Icache fill stream.
RO
ProfileMe Counter 0 Overcount.
This bit indicates a value (0-7) that must be subtracted from the counter 0
result to obtain an accurate count of the number of instructions retired in
the interval beginning three cycles after the profiled instruction reaches
pipeline stage 2 and ending four cycles after the profiled instruction is
retired.
W1C
Icache Parity Error.
This bit indicates that the Icache encountered a parity error on instruction
fetch. When a parity error is detected, the Icache is flushed, a replay trap
back to the address of the error instruction is generated, and a correctable
read interrupt is requested.
RO
Reserved for Compaq.
Trap
ITB miss
Istream Access Violation
Interrupt
Alpha 21264/EV67 Hardware Reference Manual

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