Compaq 21264 Hardware Reference Manual page 347

Cbox
data register C_DATA
, ,
described 2–11 4–3
duplicate Dcache tag array
duplicate Dcache tag array with
HW_MTPR and HW_MFPR to CSR
,
I/O write buffer 2–11
internal processor registers
,
probe queue 2–11
,
read register 5–41
shift register C_SHFT
,
victim address file 2–11
WRITE_MANY chain
WRITE_MANY chain example
WRITE_ONCE chain
,
CC cycle counter register
at power-on reset state
CC_CTL cycle counter control register
at power-on reset state
CFR_EV6CLK_DELAY Cbox CSR, defined
CFR_FRMCLK_DELAY Cbox CSR, defined
CFR_GCLK_DELAY Cbox CSR, defined
ChangeToDirtyFail, SysDc command
4–12
ChangeToDirtySuccess, SysDc command
,
4–11 4–12
,
Choice predictor 2–5
ChxToDirty, 21264/EV67 command
CLAMP public instruction
,
Clean cache block state 4–9
Clean/Shared cache block state
CleanToDirty, 21264/EV67 command
,
system probes, with
CleanVictimBlk, 21264/EV67 command
4–39
,
ClkFwdRst_H signal pin
with system initialization
,
ClkIn_x signal pins 3–4
,
Clock forwarding 7–4
CLR_MAP clear virtual-to-physical map register
5–21
at power-on reset state
CMOV instruction, special cases of
COLD reset machine state
Commands
21264/EV67 to system
system to 21264/EV67
,
when to NXM 4–38
Alpha 21264/EV67 Hardware Reference Manual
,
5–33
,
2–11
,
4–13
,
D–15
,
5–3
,
5–33
,
5–38
,
5–39
,
5–33
5–3
,
7–15
,
5–3
,
7–15
,
5–37
,
5–38
,
5–37
, , ,
4–10 4–11
, ,
4–10
,
4–12
,
B–1
,
4–10
, ,
4–22 4–40
4–41
, ,
4–22
,
3–4 4–30
,
7–7
,
,
7–15
,
2–26
,
7–17
,
4–19
,
4–26
,
Conventions xix
,
abbreviations xix
,
address xx
,
aligned xx
,
bit notation xx
,
caution xx
,
data units xxi
,
do not care xxi
,
external xxi
,
field notation xxi
,
note xxi
,
numbering xxi
,
ranges and extents xxi
,
register figures xxi
,
signal names xxi
,
unaligned xx
,
X xxi
,
CTAG 4–13
D
Data cache. See Dcache
Data merging
load instructions in I/O address space
store instructions in I/O address space
Data transfer commands, system
Data types
floating point support
,
integer supported 1–2
,
supported 1–1
,
Data units convention xxi
,
Data wrap 4–36
,
double-pumped 4–38
,
interleaved 4–37
DATA_VALID_DLY Cbox CSR, defined
dc
,
characteristics of 9–2
input pin capacitance defined
,
test load defined 9–2
voltage on signal pins
DC_CTL Dcache control register
at power-on reset state
,
error correction and
DC_PERR error status in C_STAT
DC_STAT Dcache status register
at power-on reset state
,
2–28
,
2–29
,
4–28
,
1–2
,
5–38
,
9–2
,
9–1
,
5–30
,
7–16
8–2
,
5–41
,
5–31
,
7–16
Index–3