Compaq 21264 Hardware Reference Manual page 349

ECC
64-bit data and check bit code
Dcache data single-bit correctable errors
,
for system data bus
memory/system port single-bit correctable
,
errors 8–7
,
store instructions 8–4
ENABLE_EVICT Cbox CSR
ENABLE_PROBE_CHECK Cbox CSR
,
defined 5–35
ENABLE_STC_COMMAND Cbox CSR, defined
5–35
,
Energy star certification
,
Error case summary 8–9
Error correction code. See ECC
Error detection mechanisms
,
EV6Clk_x signal pins 3–4
Evict, 21264/EV67 command
EVICT_ENABLE Cbox CSR
EXC_ADDR exception address register
,
after fault reset 7–8
at power-on reset state
EXC_SUM exception summary register
at power-on reset state
Exception and interrupt logic
Exception condition summary
External cache and system interface unit. See Cbox
,
External convention xxi
External interface initialization
EXTEST public instruction
F
F31
load instructions with
retire instructions with
,
Fast data disable mode 4–33
, ,
Fast data mode 4–30 4–31
FAST_MODE_DISABLE Cbox CSR
,
defined 5–34
,
Fault reset flow 7–8
Fault reset sequence of operations
FAULT_RESET reset machine state
Fbox
,
described 2–10
,
executed in pipeline
,
FEN fault 6–13
FetchBlk, 21264/EV67 command
,
system probes, with
Alpha 21264/EV67 Hardware Reference Manual
,
8–2
,
8–3
8–2
, ,
4–23 5–39
,
8–2
,
7–9
,
8–1
, , ,
4–13 4–22 4–39
,
7–13
,
5–8
,
7–15
,
5–13
,
7–15
,
2–8
,
A–15
,
7–14
,
B–1
,
2–23
,
2–22
,
4–30
,
7–9
,
7–18
2–16
, ,
4–22 4–39
4–41
FetchBlkSpec, 21264/EV67 command
,
Field notation convention
Floating-point arithmetic trap, pipeline abort delay
,
with 2–16
Floating-point control register
PALcode emulation of
Floating-point execution unit. See Fbox
Floating-point instructions
,
IEEE A–9
,
independent A–11
,
VAX A–11
Floating-point issue queue
Forwarding clock pin groupings
FPCR. See Floating-point control register
FQ. See Floating-point issue queue
,
FrameClk_x signal pins
G
,
GCLK 7–19
,
Global predictor 2–4
H
Heat sink center temperature
,
Heat sink specifications
HW_INT_CLR hardware interrupt clear register
5–12
at power-on reset state
,
updating D–18
HW_LD PALcode instruction
HW_MFPR PALcode instruction
HW_MTPR PALcode instruction
HW_REI PALcode instruction
HW_RET PALcode instruction
HW_ST PALcode instruction
I
I/O address space
instruction data merging
load instruction data merging
load instructions with
store instructions with
,
I/O write buffer 2–11
,
defined 2–32
, ,
4–22 4–39
xxi
,
2–36
,
6–11
,
2–7
,
E–1
,
3–5 4–30
,
10–1
10–3
,
,
7–15
, , ,
6–3 A–9 D–18
, ,
6–6 A–9
, ,
6–6 A–9
,
A–9
,
6–5
, ,
6–4 A–9
,
2–29
,
2–28
,
2–28
,
2–29
Index–5