Power Sequencing And Reset State For Signal Pins; Power-Up Timing Sequence; Signal Pin Reset State - Compaq 21264 Hardware Reference Manual

Figure 7–1 Power-Up Timing Sequence
IRQ_H
DCOK_H
Reset_L
state
WAIT_SETTLE
SromOE_L
ClkFwdRst_H
internal ClkFwdRst
TestStat_H
external Clks

7.1.1 Power Sequencing and Reset State for Signal Pins

Power sequencing and avoiding potential failure mechanisms is described in Section
9.3.
The reset state for the signal pins is listed in Table 7–2.
Table 7–2 Signal Pin Reset State
Signal
Bcache
BcAdd_H[23:4]
BcCheck_H[15:0]
BcData_H[127:0]
BcDataInClk_H[7:0]
BcDataOE_L
BcDataOutClk_x[3:0]
BcDataWr_L
BcLoad_L
BcTag_H[42:20]
BcTagDirty_H
System Interface
IRQ_H[5:0]
SysAddIn_L[14:0]
SysAddInClk_L
Alpha 21264/EV67 Hardware Reference Manual
Power-Up Reset Flow and the Reset_L and DCOK_H Pins
A0 A1
valid
a
B
WAIT_NOMINAL RAMP1 RAMP2
Reset State
Tristated
Tristated
Tristated
NA (input)
Tristated
Tristated
Tristated
Tristated
Tristated
Tristated
NA (input)
NA (input)
NA (input)
f
WAIT_ClkFwdRst0 WAIT_BiST
b
c
no min
C
g
End of BiST
Signal
BcTagInClk_H
BcTagOE_L
BcTagOutClk_x
BcTagParity_H
BcTagShared_H
BcTagValid_H
BcTagWr_L
BcVref
SysDataInClk_H[7:0]
SysDataInValid_L
SysDataOutClk_L[7:0] Tristated
Initialization and Configuration
WAIT_ClkFwdRst1 RUN
e
no min
d
BiST Fails BiST Passes
FM-06486B.FH8
Reset State
NA (input)
Tristated
Tristated
Tristated
Tristated
Tristated
Tristated
NA
(I_DC_REF)
NA (input)
NA (input)
7–3