Process Context Register; Process Context Register Fields Description - Compaq 21264 Hardware Reference Manual

Ibox IPRs
Figure 5–24 Process Context Register
63
ASN[7:0]
ASTRR[3:0]
ASTER[3:0]
FPE
PPCE
Table 5–14 describes the process context register fields.
Table 5–14 Process Context Register Fields Description
Name
Reserved
ASN[7:0]
Reserved
ASTRR[3:0]
ASTER[3:0]
Reserved
Internal Processor Registers
5–22
47 46 39 38
Extent Type Description
[63:47] — —
[46:39] RW Address space number.
[38:13] — —
[12:9] RW AST request register—used to request AST interrupts in
each of the four processor modes.
To generate a particular AST interrupt, its corresponding
bits in ASTRR and ASTER must be set, along with the
ASTE bit in IER.
Further, the value of the current mode bits in the PS register
must be equal to or higher than the value of the mode associ-
ated with the AST request.
The bit order with this field is:
[8:5] RW AST enable register—used to individually enable each of
the four AST interrupt requests.
The bit order with this field is:
[4:3] — —
User Mode
Supervisor Mode
Executive Mode
Kernel Mode
User Mode
Supervisor Mode
Executive Mode
Kernel Mode
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