Teststat_H Pin; Tap Controller State Machine - Compaq 21264 Hardware Reference Manual

TestStat_H Pin

Figure 11–1 TAP Controller State Machine
Test Logic
Reset
1
0
1
Run-Test/Idle
0
Values
shown
are for
TMS.
11.4 TestStat_H Pin
The TestStat_H pin serves two purposes. During power-up, it indicates BiST pass/fail
status. After power-up, it indicates the 21264/EV67 timeout event.
The system reset forces TestStat_H to low. Tbox forces it high during the internal BiST
and array initialization operations. During result extraction (DoResult state), the Tbox
drives it low for 16 cycles. After that, the pin remains low if the BiST has passes, other-
wise, it is asserted high and remains high until chip is reset again. Figure 11–2 pictori-
ally shows the behavior of the pin during the power-up operations.
Note:
Testability and Diagnostics
11–4
1
Select-DR-Scan
0
1
Capture-DR
0
0
Shift-DR
1
1
Exit1-DR
0
0
Pause-DR
1
0
Exit2-DR
1
Update-DR
1
0
Scan Sequence
A system designer may sample the TestStat_H pin on the first rising edge
of the SromClk_H pin to determine BiST results. After the power-up dur-
ing the normal chip operation, whenever the 21264/EV67 does not retire an
instruction for 2K CPU cycles, the pin is asserted high for 3 CPU cycles.
Select-IR-Scan
0
1
Capture-IR
Shift-IR
Exit1-IR
0
Pause-IR
0
Exit2-IR
Update-IR
1
Scan Sequence
Alpha 21264/EV67 Hardware Reference Manual
1
0
0
1
1
0
1
1
0
MK145508.AI4