Hardware Interrupt Clear Register - Hw_Int_Clr; Hardware Interrupt Clear Register; Interrupt Summary Register Fields Description - Compaq 21264 Hardware Reference Manual

Ibox IPRs
Table 5–7 describes the interrupt summary register fields.
Table 5–7 Interrupt Summary Register Fields Description
Name
Reserved
EI[5:0]
SL
CR
PC[1:0]
SI[15:1]
Reserved
ASTU, ASTS
Reserved
ASTE, ASTK
Reserved
5.2.12 Hardware Interrupt Clear Register – HW_INT_CLR
The hardware interrupt clear register (HW_INT_CLR) is a write-only register used to
clear edge-sensitive interrupt requests. See Section D.31 for more information about the
PALcode restriction concerning this register. Figure 5–19 shows the hardware interrupt
clear register.
Figure 5–19 Hardware Interrupt Clear Register
63
SL
CR
PC[1:0]
MCHK_D
FBTP
Internal Processor Registers
5–12
Extent Type Description
[63:39] — —
[38:33] RO External Interrupts
[32] RO Serial Line Interrupt
[31] RO Corrected Read Error Interrupts
[30:29] RO Performance Counter Interrupts
PC0 when PC[0] is set.
PC1 when PC[1] is set.
[28:14] RO Software Interrupts
[13:11] — —
[10],[9] RO AST Interrupts
For each processor mode, the bit is set if an associated AST
interrupt is pending. This includes the mode's ASTER and
ASTRR bits and whether the processor mode value held in the
IER_CM register is greater than or equal to the value for the
mode.
[8:5] — —
[4],[3] RO AST Interrupts
For each processor mode, the bit is set if an associated AST
interrupt is pending. This includes the mode's ASTER and
ASTRR bits and whether the processor mode value held in the
IER_CM register is greater than or equal to the value for the
mode.
[2:0] — —
33 32 31 30 29 28 27 26 25
Alpha 21264/EV67 Hardware Reference Manual
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