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Table 4–46 lists the combination of control pin assertion for RAM_TYPE C.
Table 4–46 Control Pin Assertion for RAM_TYPE C
TYPE_C
BcLoad_L
BcDataOE_L
BcDataWr_L
BcTagOE_L
BcTagWr_L
Table 4–47 lists the combination of control pin assertion for RAM_TYPE D.
Table 4–47 Control Pin Assertion for RAM_TYPE D
TYPE_D
BcLoad_L
BcDataOE_L
BcDataWr_L
BcTagOE_L
BcTagWr_L
Notes:
1. The NOP condition for RAM_TYPE B is consistent with bursting nonPentium
style SSRAMs.
2. In both
function changes from output-enable control to chip-select control.
3. In both RAM_TYPE C and RAM_TYPE D SSRAMs, the pins
BcTagOE_L
read data by providing an extra cycle of output enable.
Using these Cbox CSRs, late-write nonbursting and dual-data rate SSRAMs can be
connected to the 21264/EV67 as described in Appendix E.
4.8.4.3 BcDataInClk_H and BcTagInClk_H
The BcDataInClk_H[7:0] and BcTagInClk_H pins are used to capture tag data and
data from the Bcache data and tag RAMs respectively. Dual-data rate SSRAMs provide
a clock output with the data output pins to minimize skew between the data and clock,
thus allowing maximum bandwidth. The 21264/EV67 internally synchronizes the data
to its GCLK with clock forward receive circuitry similar to that in the system interface.
For nonDDR SSRAMs, systems can connect the Bcache data and tag output clock pins
to the Bcache data and tag input clock pins.
Alpha 21264/EV67 Hardware Reference Manual
NOP RA0
RA1
RA2
H
H
H
H
H
H
L
L
H
H
H
H
H
L
L
H
H
H
H
H
NOP
RA0
RA1
RA2
H
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
H
H
and RAM_TYPE B, the pins
RAM_TYPE A
function as an asynchronous output enable that envelopes the Bcache
RA3
NOP
NOP WA0 WA1 WA2 WA3 NOP
H
H
H
H
L
L
L
H
H
H
H
L
H
H
H
H
H
H
H
L
RA3 NOP
NOP
WA0
H
H
H
L
L
L
L
H
H
H
H
L
H
H
H
H
H
H
H
L
BcDataOE_L and BcTagOE_L
Cache and External Interfaces
Bcache Port
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
WA1 WA2 WA3 NOP
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
BcDataOE_L and
4–53
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