Software Interrupt Request Register - Sirr; Interrupt Enable And Current Processor Mode Register; Ier_Cm Register Fields Description - Compaq 21264 Hardware Reference Manual

Ibox IPRs
Figure 5–16 Interrupt Enable and Current Processor Mode Register
63
EIEN[5:0]
SLEN
CREN
PCEN[1:0]
SIEN[15:1]
ASTEN
CM[1:0]
Table 5–5 describes the interrupt enable and current processor mode register fields.
Table 5–5 IER_CM Register Fields Description
Name
Reserved
EIEN[5:0]
SLEN
CREN
PCEN[1:0]
SIEN[15:1]
ASTEN
Reserved
CM[1:0]
Reserved
5.2.10 Software Interrupt Request Register – SIRR
The software interrupt request register (SIRR) is a read-write register containing bits to
request software interrupts. To generate a particular software interrupt, its correspond-
ing bits in SIRR and IER[SIER] must both be set. Figure 5–17 shows the software
interrupt request register.
Internal Processor Registers
5–10
39 38 33 32
Extent Type Description
[63:39] — —
[38:33] RW External Interrupt Enable
[32] RW Serial Line Interrupt Enable
[31] RW Corrected Read Error Interrupt Enable
[30:29] RW Performance Counter Interrupt Enables
[28:14] RW Software Interrupt Enables
[13] RW AST Interrupt Enable
When set, enables those AST interrupt requests that are also
enabled by the value in ASTER.
[12:5] — —
[4:3] RW Current Mode
00
01
10
11
[2:0] — —
31 30 29 28
Kernel
Executive
Supervisor
User
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