Compaq 21264 Hardware Reference Manual page 351

2–16
Integer execution unit. See Ebox
,
Integer issue queue 2–6
,
pipelined 2–15
Internal processor registers
,
accessing 6–7
,
explicitly written 6–8
,
implicitly written 6–9
,
ordering access 6–9
,
paired fetch order 6–9
,
scoreboard bits for 6–8
,
INTERRUPT interrupt 6–14
INVAL_TO_DIRTY Cbox CSR
,
programming 4–23
INVAL_TO_DIRTY_ENABLE Cbox CSR
7–12
InvalToDirty, 21264/EV67 command
4–40
,
system probes, with
InvalToDirtyVic, 21264/EV67 command
4–40
IOWB. See I/O write buffer
IPRs. See Internal processor registers
IQ. See Integer issue queue
,
IRQ_H signal pins 3–5
,
Istream 2–5
Istream memory references
translation to external references
ISTREAM_BC_DBL error status in C_STAT
ISTREAM_BC_ERR error status in C_STAT
ISTREAM_MEM_DBL error status in C_STAT
5–41
ISTREAM_MEM_ERR error status in C_STAT
5–41
ISUM interrupt summary register
at power-on reset state
,
ITB 2–5
,
ITB fill 6–16
ITB miss, pipeline abort delay with
ITB_IA invalidate-all register
at power-on reset state
ITB_IAP invalidate-all (ASM=0) register
at power-on reset state
ITB_IS invalidate single register
at power-on reset state
,
ITB_MISS fault 6–14
ITB_PTE array write register
at power-on reset state
Alpha 21264/EV67 Hardware Reference Manual
,
5–1
,
4–23
, ,
5–39
, , ,
4–12 4–22
4–41
, ,
4–22
,
4–5
,
5–41
,
5–41
,
,
,
5–11
,
7–15
,
2–16
,
5–7
,
7–15
,
5–7
,
7–15
,
5–7
,
7–15
,
5–6
,
7–14
ITB_TAG array write register
at power-on reset state
IVA_FORM instruction virtual address format
,
register 5–9
at power-on reset state
J
JITTER_CMD Cbox CSR, defined
JMP misprediction, in PALcode
JSR misprediction
,
in PALcode D–15
pipeline abort delay with
JSR_COR misprediction, in PALcode
,
Junction temperature 9–1
L
Late-write non-bursting SSRAM pin assignments
E–2
LDBU instruction, normal prefetch with
LDF instruction, normal prefetch with
LDG instruction, normal prefetch with
LDQ instruction, prefetch with evict next
LDS instruction, prefetch with modify intent
LDT instruction, normal prefetch with
LDWU instruction, normal prefetch with
LDx_L instructions
in-order processing for
locking mechanism for
,
Load hit speculation 2–24
Load instructions
,
ECC with 8–3
I/O reference ordering
,
Mbox order traps 2–31
memory reference ordering
translation to external interface
,
Load queue, described 2–13
,
Load-load order trap 2–32
,
Local predictor 2–4
,
Lock mechanism 4–14
Logic symbol, the 21264/EV67
LQ. See Load queue
M
M_CTL Mbox control register
at power-on reset state
MAF. See Miss address file
MB instruction processing
,
5–6
,
7–14
,
7–15
,
5–38
,
D–15
,
2–16
,
D–15
,
,
2–23
,
2–23
,
2–23
,
2–24
,
2–23
,
2–23
,
2–23
,
4–15
,
4–14
,
2–31
,
2–31
,
4–5
,
3–2
,
5–29
,
7–16
,
2–33
Index–7