NEC Renesas V850/SC1 User Manual page 369

32-bit single-chip microcontrollers
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(d) Cautions
To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn
register during the transfer reservation period.
If the SIRBn register or the SOTBn register is accessed when the transfer reservation period is over, the
following occurs.
(i) In case of contention between transfer request clear and register access
Since request cancellation has higher priority, the next transfer request is ignored. Therefore, transfer
is interrupted, and normal data transfer cannot be performed.
Figure 11-19. Transfer Request Clear and Register Access Contention
SCKn
(I/O)
INTCSIn
interrupt
rq_clr
Reg_R/W
Remarks 1. n = 5, 6
2. rq_clr:
Internal signal. Transfer request clear signal.
Reg_R/W: Internal signal.
(SIRBn/SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was
performed.
CHAPTER 11
SERIAL INTERFACE FUNCTION
Transfer reservation period
This signal indicates that the receive data buffer register
User's Manual U15109EJ3V0UD
367

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