Pin Operations - NEC Renesas V850/SC1 User Manual

14.2 Pin Operations

During the system reset period, almost all pins are set to high impedance (except for RESET, X2, XT2, CPUREG,
V , V , ADCV , ADCGND, PORTV
DD0 DD1 DD
V /IC).
PP
Accordingly, if connected to an external memory device, be sure to attach a pull-up (or pull-down) resistor to each
pin. If such a resistor is not attached, these pins will be set to high impedance, which could damage the data in
memory devices. Likewise, make sure the pins are handled so as to prevent such effects at the signal outputs by on-
chip peripheral I/O functions and output ports.
X1
RESET
Internal system
reset signal
Figure 14-2. System Reset Timing by Watchdog Timer Overflow
X1
operation
Watchdog
timer
overflow
Internal
reset signal
Port pin
of I/O port
484
CHAPTER 14
to PORTV
DD0
Figure 14-1. System Reset Timing by RESET Signal Input
Analog delay Analog delay
Eliminated as noise
Reset is accepted
Reset period
Normal
(oscillation
stopped)
User's Manual U15109EJ3V0UD
RESET FUNCTION
, PORTGND0, PORTGND1, GND0, GND1, GND2, and
DD2
Hi-Z
Oscillation stabilization time
Analog delay
13.1 ms (@20 MHz operation)
Hi-Z
Oscillation
stabilization
time wait
Hi-Z
Reset is canceled
Normal operation
(reset processing)