Rules For Correct Setting Of Baud Rate - NEC Renesas V850/SC1 User Manual

19.13 Rules for Correct Setting of Baud Rate

The CAN protocol limit values for ensuring correct operation of FCAN are described below. If these limit values
are exceeded, a CAN protocol violation may occur, which can result in operation faults. Always make sure that
settings are within the range of limit values.
(a) 5 × BTL ≤ SPT (sampling point) ≤ 17 × BTL [4 ≤ set values of SPTR4 to SPTR0 ≤ 16]
(b) 8 × BTL ≤ DBT (data bit time) ≤ 25 × BTL [7 ≤ set values of DBTR4 to DBTR0 ≤ 24
(c) SJW (synchronization jump width) ≤ DBT – SPT
(d) 2 ≤ (DBT – SPT) ≤ 8
Remark BTL = 1/f (f
BTL
SPTR4 to SPTR0 (bits 9 to 5 of the CANn synchronization control register (CnSYNC))
DBTR4 to DBTR0 (bits 4 to 0 of the CANn synchronization control register (CnSYNC))
(1) Example of FCAN baud rate setting (when CnBRP register's TLM bit = 0)
The following is an example of how correct settings for the CnBRP register and CnSYNC register can be
calculated.
Conditions from CAN bus:
<1> CAN base clock frequency (f
<2> CAN bus baud rate:
<3> Sample point:
<4> Synchronization jump width:
First, calculate the ratio between the CAN base clock frequency and the CAN bus baud rate frequency as
shown below.
/CAN bus band rate = 16 MHz/83 kHz ≠ 192.77 ≠ 2
f
MEM
Set an even number between 2 and 128 to the CnBRP register's bits BRP5 to BRP0 as the setting for the
prescaler (CAN protocol layer basic system clock: f
register's bits DTBR4 to DBTR0 as the data bit time.
Since it is assumed that the SJW (synchronization jump width) value is 3, the maximum setting for SPT
(sample point) is the "data bit time setting minus 3" or less and 17 or less.
(SPT ≤ DBT – 3 and SPT ≤ 17)
CHAPTER 19 FCAN CONTROLLER (V850/SC3)
: CAN protocol layer basic system clock)
BTL
): 16 MHz
MEM
83 Kbps
80% or more
3 BTL
User's Manual U15109EJ3V0UD
× 3
6
), then set a value between 8 and 25 to the CnSYNC
BTL
675