Chapter 14 Reset Function; General - NEC Renesas V850/SC1 User Manual

14.1 General

There are three methods used to generate a reset signal.
(1) External reset by RESET signal input
(2) Internal reset by watchdog timer loop time detection (watchdog timer overflow)
(3) Internal reset by power-on-clear (POC)
(1) External reset by RESET signal input
When low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware
devices are reset to their initial settings. In addition, oscillation of the main clock is stopped during the reset
period, although oscillation of the subclock continues.
When the input at the RESET pin changes from low level to high level, the reset status is canceled and the CPU
resumes program execution after the oscillation stabilization time has elapsed (2
various registers should be initialized within the program as necessary.
An on-chip noise eliminator uses analog delay to prevent noise-related malfunction at the RESET pin.
(2) Internal reset by watchdog timer loop time detection
When the watchdog timer overflows, a system reset is performed and the various on-chip hardware devices are
initialized. In addition, the main clock stops oscillation during the reset period, although the subclock continues
oscillation.
The reset by the watchdog timer is released immediately after reset and the CPU resumes program execution
after the oscillation stabilization time has elapsed (2
(3) Internal reset by power-on-clear (POC)
When either of the following conditions is satisfied, a system reset is performed by power-on-clear.
•
When the supply voltage is less than 3.5 V
•
When the supply voltage is less than 2.2 V
•
When the supply voltage becomes less than 3.5 V
When any one of the conditions above is satisfied, a system reset is performed and the various on-chip hardware
devices are initialized. In addition, the main clock stops oscillation during the reset period, although the subclock
continues oscillation.
The power-on-clear reset is released after the power supply voltage reaches a certain voltage and the system
starts program execution after the oscillation stabilization time has elapsed (2
Whether the 3.5 V power-on-clear reset detection voltage is enabled or disabled is set using the POCC register
(when initial power is supplied, it is enabled).
Note The voltage values are maximum values; a system reset is actually performed at lower voltage than each.
CHAPTER 14 RESET FUNCTION
18
/f ).
XX
Note
at power application
Note
in STOP mode
Note
(other than when STOP mode is selected)
User's Manual U15109EJ3V0UD
18
/f ). The contents of the
XX
18
/f ).
XX
483