NEC Renesas V850/SC1 User Manual page 217

CLKOUT (output)
HLDRQ (input)
HLDAK (output)
A16 to A21 (output)
Note 2
A1 to A15 (output)
AD0 to AD15 (I/O)
ASTB (output)
R/W (output)
Note 2 Note 2
DSTB , RD ,
Note 2 Note 2
WRH , WRL (output)
UBEN, LBEN (output)
WAIT (input)
Notes 1. If the HLDRQ signal is inactive (high level) at this sampling timing, the bus hold state is not entered.
2. Only for the V850/SC1 and V850/SC2
3. If the bus hold status is entered after a write cycle, a high level may be output momentarily from the
R/W pin immediately before the HLDAK signal changes from high level to low level.
Remarks 1. indicates the sampling timing when the number of programmable waits is set to 0.
2. The broken lines indicate the high-impedance state.
CHAPTER 6 BUS CONTROL FUNCTION
Figure 6-10. Bus Hold Timing
T1 T2 T3
Note 1
Address
Address Data
User's Manual U15109EJ3V0UD
TH TH TH
Address
Note 3
TH TI T1
Address
Address
Undefined Address
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