Chapter 13 Dma Functions; Functions; Transfer Completion Interrupt Request - NEC Renesas V850/SC1 User Manual

13.1 Functions

The DMA (Direct Memory Access) controller transfers data between memory and peripheral I/Os based on DMA
requests sent from on-chip peripheral hardware (such as the serial interfaces, timer, or A/D converter).
This product includes six independent DMA channels that can transfer data in 8-bit and 16-bit units.
maximum number of transfers is 256 (when transferring data in 8-bit units).
After a DMA transfer has occurred a specified number of times, DMA transfer completion interrupt (INTDMA0 to
INTDMA5) requests are output individually from the various channels.
The priority levels of the DMA channels are fixed as follows for simultaneous generation of multiple DMA transfer
requests.
DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5

13.2 Transfer Completion Interrupt Request

After a DMA transfer has occurred a specified number of times and the TCn bit in corresponding DMA channel
control register is 0 to 5 (DCHC0 to DCHC5) has been set to 1, a DMA transfer completion interrupt request
(INTDMA0 to INTDMA5) for the interrupt controller occurs on each channel.
CHAPTER 13 DMA FUNCTIONS
User's Manual U15109EJ3V0UD
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