NEC Renesas V850/SC1 User Manual page 489

(2) VM45 control register (VM45C)
The detection status (detected/undetected) according to the VM45 bit of the POCS register can be output
(monitored) at the VM45/P176 pin via control by the VM45C register.
After reset: 00H
7
POCS 0
VM45C1
0
1
VM45C0
0
1
Note When using P176 as an alternate function pin, it is necessary to set the PM176 bit of the port 17
mode register (PM17) to 0 (output mode), or the P176 bit of port 17 (P17) to 0 (0 output).
(3) POC control register (POCC)
This register sets whether the 3.5 V power-on-clear reset detection voltage is enabled disabled.
However, detection of less than 2.5 V in STOP mode cannot be disabled.
Reset by power-on-clear when the initial power supply is applied is enabled, and reset by power-on-clear caused
by a subsequent voltage drop is prohibited. Reset applied through the RESET pin clears POCC to 00H.
The POCC register is set by an 8-bit memory manipulation instruction.
After reset: 00H
7
POCC 0
POCC0
0
1
CHAPTER 14 RESET FUNCTION
R/W Address: FFFFF07CH
6 5 4
0 0 0
VM45 (V 4.5 V monitor) output enabled/disabled
DD0
VM45 output at VM45/P176 pin disabled (port function)
VM45 output at VM45/P176 pin enabled
VM45 (V
DD0
High-level output when VM45 detected
Low-level output when VM45 detected
R/W Address: FFFFF076H
6 5 4
0 0 0
3.5 V power-on-clear reset detection voltage enabled/disabled
Enabled (3.5 V power-on-clear reset detection voltage is valid)
Disabled (3.5 V power-on-clear reset detection voltage is invalid)
User's Manual U15109EJ3V0UD
3 2
0 0 VM45C1
Note
4.5 V monitor) output selection
3 2
0 0
1 0
VM45C0
1 0
0 POCC0
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