NEC Renesas V850/SC1 User Manual page 656

32-bit single-chip microcontrollers
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Sync segment
Segment name
Sync segment
(Synchronization Segment)
Prop segment
(Propagation Segment)
Phase segment 1
(Phase Buffer Segment 1)
Phase segment 2
(Phase Buffer Segment 2)
SJW
(reSynchronization Jump Width)
Note IPT: Information Processing Time
IPT is a period in which the current bit level is referenced and judgement for the next processing is
performed.
IPT is indicated by the expression below using the supply clock (f
IPT = f
MEM1
(3) Data bit synchronization
• Since the receiving node has no synchronization signal, synchronization is performed using level changes
that occur on the bus.
• As for the transmitting node, data is transmitted in sync with the transmitting node's bit timing.
(a) Hardware synchronization
This is bit synchronization that is performed when the receiving node has detected a start of frame in bus
idle mode.
• When a falling edge is detected on the bus, the current bit is assigned to the sync segment and the
next bit is assigned to the prop segment. In such cases, synchronization is performed regardless of
the SJW (reSynchronization Jump Width).
• Since bit synchronization must be established after a reset or after a wakeup, hardware
synchronization is performed only at the first level change that occurs on the bus (for the second and
subsequent level changes, bit synchronization is performed as shown below).
654
CHAPTER 19
FCAN CONTROLLER (V850/SC3)
Figure 19-25. Nominal Bit Time
Nominal bit time
Prop segment
SJW
Segment length
1
1 to 8 (programmable)
1 to 8 (programmable)
Maximum value from
phase segment 1 or
Note
IPT
(IPT = 0 to 2)
1 to 4 (programmable)
× 3
User's Manual U15109EJ3V0UD
Phase segment 1
Phase segment 2
Sample point
Description
This segment begins when resynchronization occurs.
This segment is used to absorb the delays caused by
the output buffer, CAN bus, and input buffer.
It is set to return an ACK signal until phase segment 1
begins.
Prop segment time ≥ (output buffer delay) + (CAN bus
delay) + (input buffer delay)
This segment is used to compensate for errors in the
data bit time. It accommodates a wide margin or error
but slows down communication speed.
This sets the range for bit synchronization.
) to CAN.
MEM1
SJW

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