NEC Renesas V850/SC1 User Manual page 8

Page
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Deletion of indication "under development" for the following products (developed)
Throughout
µ PD703068YGJ-×××-UEN, 703069YGJ-×××-UEN
•
Addition of watch timer high-speed clock select register (WTNHC), IIC flag registers 0 and 1 (IICF0,
IICF1)
p.49 Change of minimum instruction execution time in 1.4.1 Features (V850/SC3)
p.56 Modification of description in Table 2-1 Pin I/O Buffer Power Supplies
p.66 Modification of description in Table 2-3 Pin Operation States in Various Operating Modes
pp.109, 113, 115, Modification of 3.4.8 Peripheral I/O registers
116
p.119 Addition of Remarks in 3.4.9 (2) System status register (SYS)
p.120 Change of frequency of the V850/SC3 in 4.1 (1) Main clock oscillator
pp.122, 123 Addition of Note and Caution in 4.3.1 (1) Processor clock control register (PCC)
p.123 Modification of description for setting DCLK1 and DCLK0 bits = 01B and addition to Notes in 4.3.1 (2)
Power save control register (PSC)
p.128 Modification of description on operation status of A16 to A21 pins in Table 4-1 Operating Statuses in
HALT Mode
p.129 Modification of description on operation of UART0 to UART3 in Table 4-2 Operating Statuses in IDLE
Mode
p.131 Addition of description in 4.4.4 (1) Settings and operating states
p.132 Modification of description on operation status of UART0 to UART3 in Table 4-3 Operating Statuses in
Software STOP Mode
p.135 Addition of 4.6 (1) When executing an instruction on internal ROM
p.136 Addition of Caution in 4.6 (2) When executing an instruction on external ROM
p.138 Modification of description in Table 5-1 Pin I/O Buffer Power Supplies
p.166 Addition of Caution in 5.2.8 (1) Function of P9 pins
pp.192 to 194 Addition and modification of description in Table 5-16 Setting When Port Pin Is Used for Alternate
Function
p.198 Addition of 5.4 Operation of Port Function
p.201 Addition of Note and Caution in 6.2.2 (1) System control register (SYC) (V850/SC1, V850/SC2)
p.223 Modification of description in Figure 7-2 Acknowledging Non-Maskable Interrupt Requests
p.250 Addition of 7.8.1 Interrupt request valid timing following EI instruction
p.252 Addition of 7.9 Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer
p.258 Addition and modification of description in 8.1.3 (2) Capture/compare register n0 (CR00, CR10, CR70
to CR120)
p.259 Addition and modification of description in 8.1.3 (3) Capture/compare register n1 (CR01, CR11, CR71
to CR121)
p.261 Addition to Cautions in 8.1.4 (1) 16-bit timer mode control registers 0, 1, 7 to 12 (TMC0, TMC1,
TMC7 to TMC12)
p.262 Addition to Cautions in 8.1.4 (2) Capture/compare control registers 0, 1, 7 to 12 (CRC0, CRC1,
CRC7 to CRC12)
p.275 Addition of Figure 8-6 Configuration of PPG Output and Figure 8-7 PPG Output Operation Timing
6
Major Revisions in This Edition (1/4)
User's Manual U15109EJ3V0UD
Description