NEC Renesas V850/SC1 User Manual page 297

(12) Edge detection
(a) When the TIn0 or TIn1 pin is high level immediately after a system reset
When the TIn0 or TIn1 pin is high level immediately after a system reset, if the valid edge of the TIn0 or TIn1
pin is specified as the rising edge or both rising and falling edges, and the operation of 16-bit timer/counter n
(TMn) is then enabled, the rising edge will be detected immediately. Care is therefore needed when the TIn0
or TIn1 pin is pulled up. However, when operation is enabled after being stopped, the rising or falling edge
is not detected.
(b) Sampling clock for noise elimination
The sampling clock for noise elimination differs depending on whether the TIn0 valid edge is used as a count
clock or a capture trigger. The former is sampled by f
selected using prescaler mode registers n0 or n1 (PRMn0, PRMn1). Detecting the valid edge can eliminate
short pulse width noise because a capture operation is performed only after the valid edge is sampled and a
valid level is detected twice.
Remark n = 0, 1, 7 to 12
CHAPTER 8 TIMER/COUNTER FUNCTION
User's Manual U15109EJ3V0UD
/2, and the latter is sampled by the count clock
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