NEC Renesas V850/SC1 User Manual page 703

(6) TIn timing
(T = –40 to +85°C, PORTV
A
µ µ µ µ PD703068Y, 703069Y, 703088Y, 703089Y: V
Parameter
TIn0, TIn1 high-level width
TIn0, TIn1 low-level width
TIm high-level width
TIm low-level width
Note The following cycles can be selected for T
prescaler mode registers n0 and n1 (PRMn0, PRMn1).
When n = 0 (TM0), T
When n = 1, 7 (TM1, TM7), T
When n = 8, 10, 12 (TM8, TM10, TM12), T
When n = 9, 11, (TM9, TM11), T
However, when the TIn0 valid edge is selected as the count clock, T
Remark T: 1/f
XX
TIn0, TIn1 (input)
TIm (input)
Remark n = 0, 1, 7 to 12
m = 5, 6
CHAPTER 20 ELECTRICAL SPECIFICATIONS
= 3.0 to 5.5 V,
DD
= 3.5 to 5.5 V, µ µ µ µ PD70F3089Y: V
DD
Symbol
<56> t n = 0, 1, 7 to 12
TIHn
<57> t n = 0, 1, 7 to 12
TILn
<58> t m = 5, 6
TIHm
<59> t m = 5, 6
TILm
(count clock cycle) by setting the PRMn2 to PRMn0 bits of
sam
= 2T, 4T, 16T, 64T, 256T, or 1/INTWTNI cycle
sam
= 2T, 4T, 16T, 32T, 128T, or 256T cycle
sam
= 2T, 8T, 16T, 32T, 128T, or 256T cycle
sam
= 4T, 8T, 32T, 64T, 128T or 512T cycle
sam
<56>
<58>
User's Manual U15109EJ3V0UD
Conditions MIN.
2T + 20
sam
2T + 20
sam
3T + 20
3T + 20
= 4T.
sam
<57>
<59>
= 4.0 to 5.5 V)
DD
MAX. Unit
Note
ns
Note
ns
ns
ns
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