Burst Read Mode - NEC Renesas V850/SC1 User Manual

19.14.2 Burst read mode

Burst read mode is implemented in the FCAN to enable faster access to complete messages and secure the
synchronization of data.
Burst read mode starts up automatically each time the CPU reads the M_DLCn register and data is then copied
from the message buffer area to a temporary read buffer.
Data continues to be read from the temporary buffer as long as the CPU keeps directly incrementing (+1) the read
address (in other words, when data is read in the following order: M_DLCn register → M_CTRLn register →
M_TIMEn register → M_DATAn0 to M_DATAn7 registers → M_IDLn, M_IDHn register), and reads more data.
If these linear access rules are not followed or if access is attempted to an address that is lower than the MIDHn
register's address (such as the M_CONFn register or M_STATn register), burst read mode becomes invalid.
Cautions 1. 16-bit read access is required for the entire message buffer area when using the burst read
mode. If 8-bit access (byte read operation) is attempted, burst read mode does not start up
even if the address is linearly incremented (+1) as described above.
2. Be sure to read out the value of FCAN control registers other than the M_DLCn register
before starting the burst read mode.
Remark n = 00 to 31
680
CHAPTER 19 FCAN CONTROLLER (V850/SC3)
User's Manual U15109EJ3V0UD