NEC Renesas V850/SC1 User Manual page 364

32-bit single-chip microcontrollers
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SCKn (I/O)
SIn (input)
SIOLn
register
SIRBLn
register
Reg_RD
SIRBn (dummy)
CSOTn bit
INTCSIn
interrupt
SOn (output)
L
rq_clr
trans_rq
<1>
<2>
Remarks 1. n = 5, 6
2. Reg_RD:
rq_clr:
trans_rq:
In the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer.
Following the transmission/reception completion interrupt request (INTCSIn), transfer is continued if the
SIRBn register can be read within the next transfer reservation period. If the SIRBn register cannot be
read, transfer ends and the SIRBn register does not receive the new value of the SIOn register.
The last data can be obtained by reading the SIOn register following completion of the transfer.
362
CHAPTER 11
SERIAL INTERFACE FUNCTION
Figure 11-16. Repeat Transfer (Receive-Only) Timing Chart
din-1
din-2
din-1
SIRBn (d1)
<3>
<4>
<3>
<5>
Period during
which next transfer
can be reserved
Internal signal.
This signal indicates that the receive data buffer register
(SIRBn/SIRBLn) has been read.
Internal signal. Transfer request clear signal.
Internal signal. Transfer request signal.
User's Manual U15109EJ3V0UD
din-3
din-4
din-2
din-3
SIRBn (d2)
SIRBn (d3)
<4> <3>
<4>
din-5
din-5
din-4
SIRBEn (d4)
SIOn (d5)
<6>

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