Power-On-Clear Operation - NEC Renesas V850/SC1 User Manual

14.3 Power-on-Clear Operation

The V850/SC1, V850/SC2, and V850/SC3 include a power-on-clear circuit (POC), through which low-voltage
pin voltage detection (4.2 ±0.3 V) can be performed by means of the POC status register (POCS).
detection and V
DD0
(1) POC status register (POCS)
When a power-on-clear is generated, bit 0 of the POCS register is set to 1.
In addition, if the voltage level at the V
1, enabling detection of a voltage level of less than 4.2 ±0.3 V at the V
In the case of a reset generated by the RESET pin, however, the POCM and VM45 bits retain their previous
statuses. A low-voltage state can be detected by reading the POCS register following reset cancellation.
The POCS register is read-only, using an 8-bit memory manipulation instruction. This register is reset when read.
After reset: Retained
7
POCS 0
POCM
0
1
VM45
0
1
Note This value is 03H only after a power-on-clear reset; it is not initialized by a reset from the
RESET pin.
486
CHAPTER 14 RESET FUNCTION
pin is less than 4.2 ±0.3 V, bit 1 (VM45) of the POCS register is set to
DD0
Note
R Address: FFFFF07AH
6 5 4
0 0 0
Detection of power-on-clear generation status
Power-on-clear not generated
Power-on-clear reset generated
Detection of V
V pin voltage of less than 4.5 V not detected
DD0
V pin voltage of less than 4.5 V detected
DD0
User's Manual U15109EJ3V0UD
pin.
DD0
3 2 1
0 0 VM45
pin voltage level
DD0
0
POCM