Configuration - NEC Renesas V850/SC1 User Manual

12.2 Configuration

The A/D converter includes the following hardware.
Item
Analog inputs
Registers
Control registers
(1) Successive approximation register (SAR)
This register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value
from the series resistor string, and holds the result of the comparison starting from the most significant bit (MSB).
When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion has
been completed), the contents of the SAR are transferred to the A/D conversion result register.
(2) A/D conversion result register (ADCR), A/D conversion result register H (ADCRH)
Each time A/D conversion is complete, the result of the conversion is loaded to this register from the successive
approximation register. The higher 10 bits of this register hold the result of the A/D conversion (the lower 6 bits
are fixed to 0). This register is read using a 16-bit memory manipulation instruction. RESET input sets ADCR to
0000H.
When using only higher 8 bits of the result of the A/D conversion, ADCRH is read using an 8-bit memory
manipulation instruction.
RESET input sets ADCRH to 00H.
Caution Writing to A/D converter mode register 1 (ADM1) and the analog input channel specification
register (ADS) may cause the ADCR contents to be undefined. Therefore, read the conversion
result during A/D conversion (ADCS = 1). Incorrect conversion results may be read if the
timing is other than the above.
(3) Sample & hold circuit
The sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit, and
sends the sampled data to the voltage comparator. This circuit also holds the sampled analog input signal
voltage during A/D conversion.
(4) Voltage comparator
The voltage comparator compares the analog input signal with the output voltage of the series resistor string.
(5) Series resistor string
The series resistor string is connected between ADCV
with the analog input signal.
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CHAPTER 12 A/D CONVERTER
Table 12-1. Configuration of A/D Converter
12 channels (ANI0 to ANI11)
Successive approximation register (SAR)
A/D conversion result register (ADCR)
A/D conversion result register H (ADCRH): Only higher 8 bits can
be read
A/D converter mode register 1 (ADM1)
A/D converter mode register 2 (ADM2)
Analog input channel specification register (ADS)
and ADCGND and generates a voltage for comparison
DD
User's Manual U15109EJ3V0UD
Configuration