7.7 Response Time
The following table describes the interrupt response time (from interrupt request generation to start of interrupt
servicing).
Figure 7-16. Pipeline Operation at Interrupt Request Acknowledgement
System clock
Interrupt request
Instruction 1
Instruction 2
Instruction 3
Interrupt acknowledge operation
Instruction (start instruction of
interrupt servicing routine)
INT1 to INT4: Interrupt acknowledge processing
IF
:
Invalid instruction fetch
X
ID
:
Invalid instruction decode
X
Interrupt response time (system clock)
Internal interrupt
Minimum
11
Maximum
18
CHAPTER 7
INTERRUPT/EXCEPTION PROCESSING FUNCTION
7 to 14 system clocks
IF
External interrupt
13
20
User's Manual U15109EJ3V0UD
4 system clocks
ID
EX MEM
WB
IFX IDX
IFX
INT1 INT2 INT3
INT4
IF
ID
Conditions
Time to eliminate noise (2 system clocks) is also necessary
for external interrupts, except when:
•
In IDLE/STOP mode
•
External bus is accessed
•
Two or more interrupt request non-sample instructions
are executed in succession
•
Access to interrupt control register
EX MEM WB
249