Configuration; Watchdog Timer Control Registers - NEC Renesas V850/SC1 User Manual

10.2 Configuration

The watchdog timer includes the following hardware.
Item
Control registers

10.3 Watchdog Timer Control Registers

The watchdog timer is controlled by the following registers.
• Oscillation stabilization time select register (OSTS)
• Watchdog timer clock select register (WDCS)
• Watchdog timer mode register (WDTM)
(1) Oscillation stabilization time select register (OSTS)
This register selects the oscillation stabilization time after a reset is applied or the STOP mode is released until
the oscillation is stable.
OSTS is set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 01H.
After reset: 01H
7
OSTS 0
OSTS2
0
0
0
0
1
318
CHAPTER 10 WATCHDOG TIMER FUNCTION
Table 10-3. Watchdog Timer Configuration
Oscillation stabilization time select register (OSTS)
Watchdog timer clock select register (WDCS)
Watchdog timer mode register (WDTM)
R/W Address: FFFFF380H
6 5
0 0
OSTS1 OSTS0
0 0 2
0 1 2
1 0 2
1 1 2
0 0 2
Other than above Setting prohibited
User's Manual U15109EJ3V0UD
Configuration
4 3 2
0 0 OSTS2
Oscillation stabilization time selection
Clock
20 MHz
16
/f 3.3 ms
XX
18
/f (after reset) 13.1 ms
XX
19
/f 26.2 ms
XX
20
/f 52.4 ms
XX
21
/f 104.9 ms
XX
1 0
OSTS1 OSTS0
f
XX
18.87 MHz 16 MHz
3.5 ms 4.1 ms
13.9 ms 16.4 ms
27.8 ms 32.8 ms
55.6 ms 65.5 ms
111.1 ms 131.1 ms