NEC Renesas V850/SC1 User Manual page 9

32-bit single-chip microcontrollers
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p.288
Change of description of Caution in 8.2.6 (2) One-shot pulse output via external trigger
p.319
Addition of Caution in 10.3 (2) Watchdog timer clock select register (WDCS)
p.324
Addition of description in 11.2 (2) 3-wire serial I/O mode (fixed as MSB first)
p.327
Addition to Cautions in 11.2.2 (1) Serial clock select register n (CSISn) and serial operation mode
register n (CSIMn)
p.350
Modification of description on manipulatable bits in 11.4.3 (6) Clocked serial interface read-only
receive buffer registers L5, L6 (SIRBEL5, SIRBEL6)
p.351
Modification of description on manipulatable bits in 11.4.3 (8) Clocked serial interface transmit buffer
registers L5, L6 (SOTBL6, SOTBL5)
p.352
Modification of description on manipulatable bits in 11.4.3 (10) Clocked serial interface initial transmit
buffer registers L5, L6 (SOTBFL5, SOTBFL6)
p.353
Modification of description on manipulatable bits in 11.4.3 (12) Serial I/O shift registers L5, L6 (SIOL5,
SIOL6)
pp.378, 379
Modification of description and addition to Note in 11.5.2 (1) IIC control register 0, 1 (IICC0, IICC1)
p.385
Addition of Caution in 11.5.2 (4) IIC clock expansion registers 0, 1 (IICCE0, IICCE1), IIC function
expansion registers 0, 1 (IICX0, IICX1), IIC clock select registers 0, 1 (IICCL0, IICCL1)
Addition of 11.5.12 (2) When communication reservation function is disabled (IICRSVn of IICFn
pp.421, 422
register = 1)
p.423
Change of description in 11.5.13 Cautions
p.424
Change of description in 11.5.14 (1) Master operations (1)
p.425
Addition of 11.5.14 (2) Master operations (2)
p.426
Addition of description in Figure 11-39 Slave Operation Flowchart
p.437
Addition to Cautions in 11.6.2 (1) Asynchronous serial interface mode registers 0 to 3 (ASIM0 to
ASIM3)
p.440
Addition to Cautions in 11.6.2 (4) Baud rate generator mode control registers n0, n1 (BRGMCn0,
BRGMCn1)
p.441
Addition to Cautions in Figure 11-43 ASIMn Setting (Operation Stopped Mode)
p.442
Addition to Cautions in Figure 11-44 ASIMn Setting (Asynchronous Serial Interface Mode)
p.445
Addition to Cautions in Figure 11-47 BRGMCn0 and BRGMCn1 Settings (Asynchronous Serial
Interface Mode)
p.451
Addition of description in 11.6.3 (3) (d) Reception
p.452
Deletion of description in 11.6.3 (3) (e) Receive error
p.452
Modification of Note in Figure 11-52 Receive Error Timing
p.456
Modification of Caution in 12.2 (2) A/D conversion result register (ADCR), A/D conversion result
register H (ADCRH)
p.460
Addition of Caution in 12.3 (2) Analog input channel specification register (ADS)
p.467
Modification of description in 12.6 (3) <3> Conflict between writing of ADCR and writing A/D
converter mode register 1 (ADM1) or analog input channel specification register (ADS)
p.470
Modification of description in 12.6 (8) Reading out A/D converter result register (ADCR)
p.472
Addition of 13.3 Configuration
p.477
Addition to Cautions in 13.4 (6) Start factor settings
Major Revisions in This Edition (2/4)
User's Manual U15109EJ3V0UD
Description
7

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