Cann Interrupt Pending Register (Cnintp) - NEC Renesas V850/SC1 User Manual

19.5.11 CANn interrupt pending register (CnINTP)

The CnINTP register is used to confirm the pending status of interrupts issued to the FCAN.
This register can be read/written in 8-bit or 16-bit units.
The CAN2 interrupt pending register (C2INTP) is valid only in models µ PD703089Y and 70F3089Y.
Cautions 1. When "1" is written to a bit in the CnINTP register, that bit is cleared (0). When "0" is written
to it, the bit's value does not change.
2. An interrupt occurs when the corresponding interrupt request is enabled and when no
interrupt pending bit has been set (1) for a new interrupt.
The interrupt pending bit can be set (1) only when the interrupt ready bit has been set (1) by
the CANn interrupt enable register (CnIE).
automatically cleared (0) just because the interrupt enable bit has been cleared (0). Use
software processing to clear the interrupt pending bit (0).
Whether the interrupt pending bit (1) is cleared (0) at the appropriate timing or not is
controlled by an interrupt service routine. The earlier the interrupt service routine clears (0)
the interrupt pending bit, the more quickly the interrupt occurs without losing any new
interrupts of the same type.
Remark n = 1, 2
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CHAPTER 19 FCAN CONTROLLER (V850/SC3)
User's Manual U15109EJ3V0UD
However, the interrupt pending bit is not