NEC Renesas V850/SC1 User Manual page 49

(2) Internal units
(a) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations,
arithmetic logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter
(32 bits) help accelerate processing of complex instructions.
(b) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU.
When an instruction is fetched from external memory space and the CPU does not send a bus cycle
start request, the BCU generates a prefetch address and prefetches the instruction code.
prefetched instruction code is stored in an instruction queue.
(c) ROM
This consists of a 512 KB mask ROM or flash memory mapped to the address space starting at
00000000H.
ROM can be accessed by the CPU in one clock cycle during instruction fetch.
(d) RAM
This consists of a 24 KB RAM mapped to the address space starting at FFFF9000H.
RAM can be accessed by the CPU in one clock cycle during data access.
(e) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP9) from on-chip peripheral
hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt
requests, and multiplexed servicing control can be performed for interrupt sources.
(f) Clock generator (CG)
The clock generator includes two types of oscillators: one for the main clock (f
subclock (f ), generates five types of clocks (f
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the operating clock for the CPU (f
(g) Timer/counter
A ten-channel 16-bit timer/event counter is incorporated, enabling measurement of pulse intervals and
frequency as well as programmable pulse output.
(h) Watch timer
This timer counts the reference time period (0.5 second) for counting the clock (the 32.768 kHz subclock
or the 8.388 MHz main clock). At the same time, the watch timer can be used as an interval timer for the
main clock.
(i) Watchdog timer
A watchdog timer is provided to detect inadvertent program loops and system abnormalities, etc.
It can also be used as an interval timer.
When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an
overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM)
after an overflow occurs.
CHAPTER 1 INTRODUCTION
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