Interval Of Occurrence Of Interrupt For Iebus Control - NEC Renesas V850/SC1 User Manual

18.5.5 Interval of occurrence of interrupt for IEBus control

Each control interrupt must occur at each point of communication and perform the necessary processing by the
time the next interrupt occurs. Therefore, the CPU must control the IEBus control block, taking the shortest time of
this interrupt into consideration.
The locations at which the following interrupts may occur are indicated by ↑ in the field where it may occur. ↑ does
not mean that the interrupt occurs at each of the points indicated by ↑. If an error interrupt (timing error, parity error,
or ACK error) occurs, the IEBus internal circuit is initialized. As a result, the following interrupt does not occur in that
communication frame.
(1) Master transmission
Figure 18-21. Master Transmission (Interval of Interrupt Occurrence)
Broad-
Start bit
casting
t1 T T
Communication
starts
Data P A Data
T U
Remarks 1. T: Timing error
A: ACK error
U: Underrun error
: Data set interrupt (INTIE1)
2. End of frame occurs at the end of 32-byte data.
Communication starts – timing error
Communication starts – communication start interrupt
Communication start interrupt – timing error
Communication start interrupt – end of communication
Transmission data request interrupt interval
CHAPTER 18 IEBus CONTROLLER (V850/SC2)
Master address P Slave address
T
t2
Data P A
T A
t4
End of communication
End of frame
Item
User's Manual U15109EJ3V0UD
P A Control P A
T A T
t3
T
Communication
start interrupt
Symbol
t1
t2
t3
t4
t5
Telegraph
P A Data P A
length
A T A T
t4
t5
(IEBus: at 6.29 MHz)
MIN. Unit
µ s
Approx. 93
µ s
Approx. 1282
µ s
Approx. 15
µ s
Approx. 1012
µ s
Approx. 375
U
555