NEC Renesas V850/SC1 User Manual page 283

Figure 8-15. Timing of Pulse Width Measurement with Free-Running Counter and
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70Q FRXQW
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7,Q SLQ LQSXW
9DOXH ORDGHG
WR &5Q
9DOXH ORDGHG
WR &5Q
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Remark n = 0, 1, 7 to 12
(4) Pulse width measurement by restarting
When the valid edge of the TIn0 pin is detected, the pulse width of the signal input to the TIn0 pin can be
measured by clearing 16-bit timer register n (TMn) once and then resuming counting after loading the count
value of TMn to 16-bit capture/compare register n1 (CRn1) (see Figure 8-17).
The edge is specified by bits 4 and 5 (ESn00 and ESn01) of prescaler mode register n0 (PRMn0). The rising or
falling edge can be specified.
The valid edge is detected through sampling at a count clock cycle selected by prescaler mode registers n0 and
n1 (PRMn0, PRMn1) and the capture operation is not performed until the valid level is detected two times,
eliminating noise with a short pulse width.
Caution If the valid edge of the TIn0 pin is specified to be both the rising and falling edges,
capture/compare register n0 (CRn0) cannot perform a capture operation.
Remark n = 0, 1, 7 to 12
CHAPTER 8 TIMER/COUNTER FUNCTION
Two Capture Registers (with Rising Edge Specified)
W
'
+ + D 0 + 1
'
' − ' × W
User's Manual U15109EJ3V0UD
' '
D 1 + 1 ))))+ +
'
+ − ' ' × W
'
D 2 + 1
'
'
' − ' × W
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