NEC mPD703068Y Manuals

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NEC mPD703068Y User Manual (739 pages)

32-Bit Single-Chip Microcontrollers

Brand: NEC | Category: Microcontrollers | Size: 3.6 MB

Table of Contents
15
Chapter 1 Introduction

36
General

36
V850/Sc1

37
V850/Sc2

44
V850/Sc3

51
Chapter 2 Pin Functions

58
List of Pin Functions

58
Pin States

68
Description of Pin Functions

69
Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins

84
Pin I/O Circuits

87
Chapter 3 Cpu Functions

88
Features

88
CPU Register Set

89
- Program Register Set
  90
- System Register Set
  91
Operating Modes

94
Address Space

95
- CPU Address Space
  95
- Imaging
  96
- Address Space Imaging
  96
  - Wrap-Around of CPU Address Space
    97
- Program Space
  97
- Data Space
  97
  - Memory Map
    98
  - Area
    99
- Internal Rom/Flash Memory Area
  99
- Internal RAM Area
  101
- On-Chip Peripheral I/O Area
  102
- External Memory Area (When Expanded to 64 KB, 256 KB, or 1 MB)
  103
- External Memory Area (When Expanded to 4 MB)
  104
  - External Expansion Mode
    105
  - Recommended Use of Address Space
    108
- Application of Wrap-Around
  108
- Recommended Memory Map (Flash Memory Version)
  109
  - Peripheral I/O Registers
    110
  - Specific Registers
    120
Chapter 4 Clock Generation Function

122
General

122
Configuration

123
Clock Output Function

123
- Clock Generator
  123
  - Control Registers
    124
Power Save Functions

127
- General
  127
- HALT Mode
  128
- IDLE Mode
  131
- Software STOP Mode
  133
Oscillation Stabilization Time

136
Cautions on Power Save Function

137
Chapter 5 Port Functions

140
Port Configuration

140
Port Pin Functions

142
- Port 0
  142
- Block Diagram of P00 to P07
  145
  - Port 1
    146
- Block Diagram of P10 and P12
  148
- Block Diagram of P11, P13 to P15, and P17
  149
- Block Diagram of P16
  150
  - Port 2
    151
- Block Diagram of P20 and P22
  153
- Block Diagram of P21 and P23 to P27
  154
  - Port 3
    155
- Block Diagram of P30 to P37
  158
  - Ports 4 and 5
    159
- Block Diagram of P40 to P47 and P50 to P57
  161
  - Port 6
    162
- Block Diagram of P60 to P65
  164
  - Ports 7 and 8
    165
- Block Diagram of P70 to P77 and P80 to P83
  166
  - Port 9
    167
- Block Diagram of P90 to P96
  169
  - Port 10
    170
- Block Diagram of P100 to P107
  172
  - Port 11
    173
- Block Diagram of P110 and P114 to P117
  176
- Block Diagram of P111 to P113
  177
  - Port 12
    178
- Block Diagram of P120 to P125
  180
- Block Diagram of P126 and P127
  181
  - Port 13
    182
- Block Diagram of P130 to P133
  183
  - Port 14
    184
- Block Diagram of P140 to P147
  186
  - Port 15
    187
- Block Diagram of P150 to P157
  189
  - Port 17
    190
- Block Diagram of P170 to P175
  192
- Block Diagram of P176
  193
Setting When Port Pin Is Used for Alternate Function

194
Operation of Port Function

200
- Writing Data to I/O Port
  200
- Reading Data from I/O Port
  200
Chapter 6 Bus Control Function

201
Features

201
Bus Control Pins and Control Register

202
- Bus Control Pins
  202
- Control Register
  203
Bus Access

203
- Number of Access Clocks
  203
- Bus Width
  204
Memory Block Function

205
Wait Function

206
Idle State Insertion Function

208
Bus Hold Function

209
- Outline of Function
  209
- Bus Hold Procedure
  210
- Operation in Power Save Mode
  210
Bus Timing

211
Bus Priority

218
Memory Boundary Operation Condition

218
- Program Space
  218
- Data Space
  218
Chapter 7 Interrupt/Exception Processing Function

219
Outline

219
- Features
  219
Non-Maskable Interrupts

223
- Operation
  224
- Restore
  226
- NP Flag
  227
- Noise Eliminator of NMI Pin
  227
- Edge Detection Function of NMI Pin
  228
Maskable Interrupts

229
- Operation
  229
- Restore
  231
- Priorities of Maskable Interrupts
  232
- Interrupt Control Register (Xxicn)
  235
- In-Service Priority Register (ISPR)
  239
- ID Flag
  239
- Watchdog Timer Mode Register (WDTM)
  240
- Noise Elimination
  240
- Edge Detection Function
  242
Software Exceptions

243
- Operation
  243
- Restore
  244
- EP Flag
  245
Exception Trap

246
- Illegal Op Code Definition
  246
- Operation
  246
- Restore
  247
Priority Control

248
- Priorities of Interrupts and Exceptions
  248
- Multiple Interrupt Servicing
  249
Response Time

251
Periods in Which Interrupts Are Not Acknowledged

252
- Interrupt Request Valid Timing Following EI Instruction
  252
Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer

254
Key Interrupt Function

255
Chapter 8 Timer/Counter Function

257
16-Bit Timer (TM0, TM1, TM7 to TM12)

257
- Outline
  257
- Function
  257
- Configuration
  259
- Timer 0, 1, 7 to 12 Control Registers
  262
16-Bit Timer (TM0, TM1, TM7 to TM12) Operation

274
- Operation as Interval Timer
  274
- PPG Output Operation
  276
- Pulse Width Measurement
  278
- Operation as External Event Counter
  285
- Operation as Square-Wave Output
  287
- Operation as One-Shot Pulse Output
  288
- Cautions
  293
16-Bit Timer (TM5, TM6)

298
- Functions
  298
- Configuration
  299
- Timer N Control Registers
  300
16-Bit Timer (TM5, TM6) Operation

304
- Operation as an Interval Timer
  304
- Operation as External Event Counter
  306
- Operation as Square-Wave Output
  307
- Operation as 16-Bit PWM Output
  308
- Cautions
  310
CHAPTER 10 Function

311
Chapter 9 Watch Timer Function

311
Configuration

312
Watch Timer Control Register

313
Operation

315
- Operation as Watch Timer
  315
- Operation as Interval Timer
  316
- Cautions
  317
Watchdog Timer Function

318
Functions

318
Configuration

320
Watchdog Timer Control Registers

320
Operation

323
- Operation as Watchdog Timer
  323
- Operation as Interval Timer
  324
Standby Function Control Register

325
Chapter 11 Serial Interface Function

326
Overview

326
3-Wire Serial I/O (CSI0, CSI2, CSI3): 8 Bits

326
- Configuration
  327
- Csin Control Registers
  328
- Operations
  330
3-Wire Serial I/O (CSI4): 8 to 16 Bits Variable

333
- Configuration
  333
- CSI4 Control Registers
  336
- Operations
  340
3-Wire Serial I/O (CSI5, CSI6): 8 or 16 Bits

345
- Features
  345
- Configuration
  346
- Control Registers
  348
- Operation
  356
- Output Pins
  371
- I 2 C Bus
  372
- Configuration
  375
  - I 2 C Control Registers
    377
  - I 2 C Bus Mode Functions
    390
- I C Bus Definitions and Control Methods
  391
- C Interrupt Requests (Intiicn)
  398
- Interrupt Request (Intiicn) Generation Timing and Wait Control
  416
- Address Match Detection Method
  417
- Error Detection
  417
- Extension Code
  417
- Arbitration
  418
- Wakeup Function
  419
- Communication Reservation
  420
- Cautions
  425
- Communication Operations
  426
- Timing of Data Communication
  429
Asynchronous Serial Interface (UART0 to UART3)

436
- Configuration
  436
- Uartn Control Registers
  438
- Operations
  443
- Standby Function
  455
Chapter 12 A/D Converter

456
Function

456
Configuration

458
Control Registers

460
Operation

463
- Basic Operation
  463
- Input Voltage and Conversion Result
  465
- A/D Converter Operation Mode
  466
Low-Power-Consumption Mode

469
Cautions

469
Chapter 13 Dma Functions

473
Functions

473
Transfer Completion Interrupt Request

473
Configuration

474
Control Registers

475
Operation

481
Cautions

482
Chapter 14 Reset Function

485
General

485
Pin Operations

486
Power-On-Clear Operation

488
Chapter 15 Regulator

490
Outline

490
Operation

490
Chapter 16 Rom Correction Function

491
General

491
ROM Correction Peripheral I/O Registers

492
CHAPTER 17 FLASH MEMORY ( Μ Μ Μ Μ PD70F3089Y)

495
Features

495
- Erasing Unit
  495
- Write/Read Time
  496
Writing with Flash Programmer

496
Programming Environment

499
Communication Mode

499
Pin Connection

502
- VPP Pin
  502
- Serial Interface Pin
  503
- RESET Pin
  505
- Port Pins (Including NMI)
  505
- Other Signal Pins
  505
- Power Supply
  505
Programming Method

506
- Flash Memory Control
  506
- Flash Memory Programming Mode
  506
- Selection of Communication Mode
  507
- Communication Command
  507
CHAPTER 18 Iebus CONTROLLER (V850/SC2)

509
Iebus Controller Function

509
- Communication Protocol of Iebus
  509
- Determination of Bus Mastership (Arbitration)
  510
- Communication Mode
  510
- Communication Address
  510
- Broadcast Communication
  511
- Transfer Format of Iebus
  511
- Transfer Data
  520
- Bit Format
  523
Iebus Controller Configuration

524
Internal Registers of Iebus Controller

526
- Internal Register List
  526
- Internal Registers
  527
Interrupt Operations of Iebus Controller

546
- Interrupt Control Block
  546
- Interrupt Source List
  547
- Communication Error Cause Processing List
  548
Interrupt Generation Timing and Main CPU Processing

550
- Master Transmission
  550
- Master Reception
  552
- Slave Transmission
  554
- Slave Reception
  556
- Interval of Occurrence of Interrupt for Iebus Control
  557
Chapter 19 Fcan Controller (V850/Sc3)

561
Features

561
Overview of Functions

561
Configuration

562
Internal Registers of FCAN Controller

564
- Configuration of Messages and Buffers
  564
- List of FCAN Registers
  565
Control Registers

578
Cautions Regarding Bit Set/Clear Function

630
Time Stamp Function

632
Message Processing

635
- Message Transmission
  636
- Message Reception
  637
Mask Function

638
Protocol

640
- Frame Format
  640
- Frame Types
  641
- Data Frame and Remote Frame
  641
- Error Frame
  649
- Overload Frame
  650
Functions

651
- Determination of Bus Priority
  651
- Bit Stuffing
  651
- Multimasters
  651
- Multi-Cast
  651
- CAN Sleep Mode/Can Stop Mode Function
  652
- Error Control Function
  652
- Baud Rate Control Function
  655
Operations

658
- Initialization Processing
  658
- Transmit Setting
  670
- Receive Setting
  671
- CAN Sleep Mode
  674
- CAN Stop Mode
  676
Rules for Correct Setting of Baud Rate

677
Ensuring Data Consistency

681
- Sequential Data Read
  681
- Burst Read Mode
  682
Interrupt Conditions

683
- Interrupts that Occur for FCAN Controller
  683
- Interrupts that Occur for Global CAN Interface
  683
How to Shutdown FCAN Controller

684
Cautions on Use

684
Chapter 20 Electrical Specifications

686
Chapter 21 Package Drawing

714
Chapter 22 Recommended Soldering Conditions

715
Appendix Aregister Index

716
Appendix Blist of Instruction Sets

727
Appendix Crevision History

734

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NEC mPD703068Y Manuals

NEC mPD703068Y User Manual (739 pages)

Table of Contents

Chapter 1 Introduction

General

V850/Sc1

V850/Sc2

V850/Sc3

Chapter 2 Pin Functions

List of Pin Functions

Pin States

Description of Pin Functions

Pin I/O Circuit Types, I/O Buffer Power Supply and Connection of Unused Pins

Pin I/O Circuits

Chapter 3 Cpu Functions

Features

CPU Register Set

Operating Modes

Address Space

Chapter 4 Clock Generation Function

General

Configuration

Clock Output Function

Power Save Functions

Oscillation Stabilization Time

Cautions on Power Save Function

Chapter 5 Port Functions

Port Configuration

Port Pin Functions

Setting When Port Pin Is Used for Alternate Function

Operation of Port Function

Chapter 6 Bus Control Function

Features

Bus Control Pins and Control Register

Bus Access

Memory Block Function

Wait Function

Idle State Insertion Function

Bus Hold Function

Bus Timing

Bus Priority

Memory Boundary Operation Condition

Chapter 7 Interrupt/Exception Processing Function

Outline

Non-Maskable Interrupts

Maskable Interrupts

Software Exceptions

Exception Trap

Priority Control

Response Time

Periods in Which Interrupts Are Not Acknowledged

Bit Manipulation Instruction of Interrupt Control Register on DMA Transfer

Key Interrupt Function

Chapter 8 Timer/Counter Function

16-Bit Timer (TM0, TM1, TM7 to TM12)

16-Bit Timer (TM0, TM1, TM7 to TM12) Operation

16-Bit Timer (TM5, TM6)

16-Bit Timer (TM5, TM6) Operation

CHAPTER 10 Function

Chapter 9 Watch Timer Function

Configuration

Watch Timer Control Register

Operation

Watchdog Timer Function

Functions

Configuration

Watchdog Timer Control Registers

Operation

Standby Function Control Register

Chapter 11 Serial Interface Function

Overview

3-Wire Serial I/O (CSI0, CSI2, CSI3): 8 Bits

3-Wire Serial I/O (CSI4): 8 to 16 Bits Variable

3-Wire Serial I/O (CSI5, CSI6): 8 or 16 Bits

Asynchronous Serial Interface (UART0 to UART3)

Chapter 12 A/D Converter

Function

Configuration

Control Registers

Operation