NEC Renesas V850/SC1 User Manual page 525

(a) CPU interface block
This is a control block that interfaces between the CPU (V850/SC2) and the IEBus.
(b) Interrupt control block
This control block transfers interrupt request signals from the IEBus to the CPU.
(c) Internal registers
These registers set data to the control registers and fields that control the IEBus (for the internal registers,
refer to 18.3 Internal Registers of IEBus Controller).
(d) Bit processing block
This block generates and disassembles bit timing, and mainly consists of a bit sequence ROM, 8-bit preset
timer, and comparator.
(e) Field processing block
This block generates each field in the communication frame, and mainly consists of a field sequence
ROM, 4-bit down counter, and comparator.
(f) IEBus interface block
This is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register,
conflict detector, parity detector, parity generator, and ACK/NACK generator.
CHAPTER 18 IEBus CONTROLLER (V850/SC2)
User's Manual U15109EJ3V0UD
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