NEC Renesas V850/SC1 User Manual page 29

Figure No.
Regulator ( µ PD70F3089Y)............................................................................................................................ 488
15-1
16-1 Block Diagram of ROM Correction ................................................................................................................ 489
16-2 ROM Correction Operation and Program Flow ............................................................................................. 492
17-1 Example of Wiring of Adapter for Flash Programming (FA-144GJ-UEN)...................................................... 495
17-2 Environment Required for Writing Programs to Flash Memory ..................................................................... 497
17-3 Communication with Dedicated Flash Programmer (UART0) ....................................................................... 497
17-4 Communication with Dedicated Flash Programmer (CSI0)........................................................................... 498
Communication with Dedicated Flash Programmer (CSI0 + HS) .................................................................. 498
17-5
17-6 V Pin Connection Example ........................................................................................................................ 500
PP
17-7 Conflict of Signals (Serial Interface Input Pin)............................................................................................... 501
17-8 Malfunction of Other Device .......................................................................................................................... 502
17-9 Conflict of Signals (RESET Pin) .................................................................................................................... 503
17-10 Procedure for Manipulating Flash Memory ................................................................................................... 504
17-11 Flash Memory Programming Mode ............................................................................................................... 504
17-12 Communication Command ............................................................................................................................ 505
18-1 IEBus Transfer Signal Format ....................................................................................................................... 509
18-2 Master Address Field .................................................................................................................................... 510
18-3 Slave Address Field ...................................................................................................................................... 511
18-4 Control Field .................................................................................................................................................. 513
18-5 Telegraph Length Field ................................................................................................................................. 515
18-6 Data Field ...................................................................................................................................................... 516
18-7 Bit Configuration of Slave Status................................................................................................................... 519
18-8 Configuration of Lock Address ...................................................................................................................... 520
18-9 Bit Format of IEBus ....................................................................................................................................... 521
18-10 IEBus Controller Block Diagram.................................................................................................................... 522
18-11 Interrupt Generation Timing (for (1), (3), and (4)).......................................................................................... 530
18-12 Interrupt Generation Timing (for (2) and (5)) ................................................................................................. 531
18-13 Timing of INTIE2 Interrupt Generation in Locked State (for (4) and (5)) ....................................................... 531
18-14 Timing of INTIE2 Interrupt Generation in Locked State (for (3)) ................................................................... 531
18-15 Example of Broadcast Communication Flag Operation ................................................................................ 535
18-16 Configuration of Interrupt Control Block ........................................................................................................ 544
18-17 Master Transmission ..................................................................................................................................... 548
18-18 Master Reception .......................................................................................................................................... 550
18-19 Slave Transmission ....................................................................................................................................... 552
18-20 Slave Reception ............................................................................................................................................ 554
LIST OF FIGURES (6/8)
Title
User's Manual U15109EJ3V0UD
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