Internal Registers - NEC Renesas V850/SC1 User Manual

18.3.2 Internal registers

The internal registers incorporated in the IEBus controller are described below.
(1) IEBus control register (BCR)
After reset: 00H
BCR ENIEBUS MSTRQ
ENIEBUS
MSTRQ
ALLRQ
ENSLVTX
ENSLVRX
Cautions 1. While the IEBus is operating as the master, writing to the BCR register (including bit
manipulation instructions) is disabled until either the end of that communication or
frame, or until communication is stopped by the occurrence of an arbitration-loss
communication error. Master requests cannot therefore be multiplexed. However, if the
IEBus is specified as a slave while a master request is being held pending, the BCR can
be written to at the end of communication to clear the communication end/frame end flag.
This is also the case when communication has been forcibly stopped (ENIEBUS flag = 0).
2. If a bit manipulation instruction for the BCR register conflicts with a hardware reset of the
MSTRQ flag, the BCR register may not operate normally. The following countermeasures
are recommended in this case.
• • • • Because the hardware reset is instigated in the acknowledgement period of the slave
address field, be sure to observe Caution 1 of (b) Master request flag (MSTRQ) below.
• • • • Be sure to observe the caution above regarding writing to the BCR register.
CHAPTER 18 IEBus CONTROLLER (V850/SC2)
RW Address: FFFFF3E0H
<7> <6> <5>
ALLRQ ENSLVTX ENSLVRX
0 IEBus unit stopped
1 IEBus unit active
0 IEBus unit not requested as master
1 IEBus unit requested as master
0 Individual communication requested
1 Broadcast communication requested
0 Slave transmission disabled
1 Slave transmission enabled
0 Slave reception disabled
1 Slave reception enabled
User's Manual U15109EJ3V0UD
<4> <3> 2
0
Communication enable flag
Master request flag
Broadcast request flag
Slave transmission enable flag
Slave reception enable flag
1 0
0 0
525