Rom Correction Peripheral I/O Registers; Correction Control Register (Corcn); Correction Request Register (Corrq) - NEC Renesas V850/SC1 User Manual

16.2 ROM Correction Peripheral I/O Registers

16.2.1 Correction control register (CORCN)

CORCN controls whether or not the instruction of the correction address is replaced with the JMP r0 instruction
when the correction address set to the correction address register (CORADn) matches the fetch address (n = 0 to 3).
Whether match detection by a comparator is enabled or disabled can be set for each channel.
CORCN can be set by an 8-bit or 1-bit memory manipulation instruction.
After reset: 00H
7
CORCN 0
CORENn
0
1
Remark n = 0 to 3

16.2.2 Correction request register (CORRQ)

CORRQ saves the channel in which ROM correction occurred. The JMP r0 instruction makes the program jump to
00000000H after the correction address matches the fetch address. At this time, the program can judge the following
cases by reading CORRQ.
• Reset input:
• ROM correction generation:
• Branch to 00000000H by user program: CORRQ = 00H
After reset: 00H
7
CORRQ 0
Note
CORRQn
0
1
Note The CORRQn bit is cleared by a "write 0" instruction.
Remark n = 0 to 3
490
CHAPTER 16 ROM CORRECTION FUNCTION
R/W Address: FFFFF36CH
6 5
0 0
CORADn register and fetch address match detection control (n = 0 to 3)
Match detection disabled
Match detection enabled
CORRQ = 00H
CORRQn bit = 1 (n = 0 to 3)
R/W Address: FFFFF36EH
6 5
0 0
Channel n ROM correction request flag
No ROM correction request occurred.
ROM correction request occurred.
User's Manual U15109EJ3V0UD
4 <3> <2>
0 COREN3 COREN2
4 <3> <2>
0 CORRQ3 CORRQ2
<1> <0>
COREN1 COREN0
<1> <0>
CORRQ1 CORRQ0