Software Exceptions; Operation - NEC Renesas V850/SC1 User Manual

7.4 Software Exceptions

A software exception is generated when the CPU executes the TRAP instruction, and can be always
acknowledged.
• TRAP instruction format: TRAP vector (where vector is 0 to 1FH)
For details of the instruction function, refer to the V850 Series Architecture User's Manual.

7.4.1 Operation

If a software exception occurs, the CPU performs the following processing, and transfers control to the handler
routine:
(1) Saves the restored PC to EIPC.
(2) Saves the current PSW to EIPSW.
(3) Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
(4) Sets the EP and ID bits of the PSW.
(5) Loads the handler address (00000040H or 00000050H) of the software exception routine in the PC, and
transfers control.
How a software exception is processed is shown below.
CPU processing
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 7-10. Software Exception Processing
TRAP instruction
EIPC restored PC
EIPSW PSW
ECR.EICC exception code
PSW.EP 1
PSW.ID 1
PC handler address
Exception processing
User's Manual U15109EJ3V0UD
Handler address:
00000040H (Vector = 0nH)
00000050H (Vector = 1nH)
241