Ensuring Data Consistency; Sequential Data Read - NEC Renesas V850/SC1 User Manual

32-bit single-chip microcontrollers
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19.14 Ensuring Data Consistency

When the CPU reads data from CAN message buffers, it is essential for the read data to be consistent.
Two methods are used to ensure data consistency: sequential data read and burst read mode.

19.14.1 Sequential data read

When the CPU performs sequential access of a message buffer, data is read from the buffer in the order shown in
Figure 19-74 below.
Only the FCAN internal operation can set the M_STATn register's DN bit (1) and only the CPU can clear it (0), so
during the read operation the CPU must be able to check whether or not any new data has been stored in the
message buffer.
Remark
n = 00 to 31
CHAPTER 19
FCAN CONTROLLER (V850/SC3)
Figure 19-52. Sequential Data Read
Read CPU
Clear DN flag
clear DN = 1, set DN = 0
(SC_STATn)
Read data from
message buffer
DN = 0
(M_STATn)
Yes
End of CPU's read operation
User's Manual U15109EJ3V0UD
No
679

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