NEC Renesas V850/SC1 User Manual page 560

32-bit single-chip microcontrollers
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(4) Slave reception
Figure 18-24. Slave Reception (Interval of Interrupt Occurrence)
Start bit
t1
T
Communication start
A
Data
T
t5
Remarks 1. T: Timing error
P: Parity error
A: ACK error
O: Overrun error
: Data set interrupt (INTIE1)
2. End of frame occurs at the end of 32-byte data.
Communication starts – timing error
Communication starts – communication start interrupt
Communication start interrupt – timing error
Communication start interrupt – end of communication
Receive data read interval
558
CHAPTER 18
IEBus CONTROLLER (V850/SC2)
Broad-
Master address
P
Slave address
casting
T
T
P
t2
P A
Data
Data
P A
O
T
P
t4
End of communication
End of frame
Item
User's Manual U15109EJ3V0UD
P A
Control
P A
T
T
P
t3
A
P T
Communication
start interrupt
O A
P
Symbol
t1
t2
t3
t4
t5
Telegraph
P A
Data
P
length
A
T
P
A
T
P
t4
(IEBus: at 6.29 MHz)
MIN.
Unit
µ s
Approx. 96
µ s
Approx. 1192
µ s
Approx. 15
µ s
Approx. 1012
µ s
Approx. 375

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