Operation - NEC Renesas V850/SC1 User Manual

13.5 Operation

When a DMA transfer request is generated during CPU processing, DMA transfer is started after the current CPU
processing has finished. Regardless of the transfer direction, 4 CPU clocks (f
The 4 CPU clocks are divided as follows.
• Internal RAM access: 1 clock
• Peripheral I/O access: 3 clocks
After one DMA transfer (8/16 bits) ends, control always shifts to the CPU processing.
A DMA transfer operation timing chart is shown below.
DMA transfer processing signal
DMA transfer acknowledge signal
Processing format
Access destination for transfer from
internal RAM to peripheral I/O
Access destination for transfer from
peripheral I/O to internal RAM
Remark n = 0 to 5
If two or more DMA transfer requests are generated simultaneously, the DMA transfer requests are executed in
accordance with the following priority order: DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5. While a higher
priority DMA transfer request is being executed, the lower priority DMA transfer requests are held pending. After the
higher priority DMA transfer ends, control always shifts to the CPU processing once, and then the lower priority DMA
transfer is executed.
The processing when the transfer requests DMA0 to DMA5 are generated simultaneously is shown below.
CHAPTER 13 DMA FUNCTIONS
Figure 13-3. DMA Transfer Operation Timing
f
CPU
CPU processing
User's Manual U15109EJ3V0UD
) are required for one DMA transfer.
CPU
DMA transfer
CPU processing
processing
RAM Peripheral I/O
Peripheral I/O RAM
INTDMAn occurs when a DBCn
register borrow occurs
479 479