NEC Renesas V850/SC1 User Manual page 440

(2) Asynchronous serial interface status registers 0 to 3 (ASIS0 to ASIS3)
When a receive error occurs in asynchronous serial interface mode, these registers indicate the type of error.
ASISn can be read using an 8-bit or 1-bit memory manipulation instruction.
RESET input sets these registers to 00H.
After reset: 00H
7
ASISn 0
(n = 0 to 3)
PEn
0
1
FEn
0
1
OVEn
0
1
Notes 1. Even if the stop bit length has been set as two bits by setting bit 2 (SLn) of asynchronous serial
interface mode register n (ASIMn), stop bit detection during a receive operation only applies to a stop
bit length of 1 bit.
2. Be sure to read the contents of receive buffer register n (RXBn) when an overrun error has occurred.
Until the contents of RXBn are read, further overrun errors will occur when receiving data.
438
CHAPTER 11 SERIAL INTERFACE FUNCTION
R Address: ASIS0:
6 5
0 0
No parity error
Parity error
(Transmit data parity does not match)
No framing error
Note 1
Framing error
(Stop bit not detected)
No overrun error
Note 2
Overrun error
(Next receive operation was completed before data was read from receive buffer register)
User's Manual U15109EJ3V0UD
FFFFF302H ASIS1:
ASIS2: FFFFF232H ASIS3:
4 3
0 0
Parity error flag
Framing error flag
Overrun error flag
FFFFF312H
FFFFF2B2H
<2> <1> <0>
PEn FEn OVEn