Ppg Output Operation - NEC Renesas V850/SC1 User Manual

32-bit single-chip microcontrollers
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8.2.2 PPG output operation

TMn can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register n
(TMCn) and capture/compare control register n (CRCn) as shown in Figure 8-5.
The PPG output function outputs a square-wave from the TOn pin with a cycle specified by the count value preset
to 16-bit capture/compare register n0 (CRn0) and a pulse width specified by the count value preset to 16-bit
capture/compare register n1 (CRn1).
Remark
n = 0, 1, 7 to 12
Figure 8-5. Control Register Settings in PPG Output Operation
(a) 16-bit timer mode control registers 0, 1, 7 to 12 (TMC0, TMC1, TMC7 to TMC12)
TMCn
0
0
(b) Capture/compare control registers 0, 1, 7 to 12 (CRC0, CRC1, CRC7 to CRC12)
CRCn
0
0
(c) 16-bit timer output control registers 0, 1, 7 to 12 (TOC0, TOC1, TOC7 to TOC12)
OSPTn
TOCn
0
0
Cautions 1. Make sure that CRn0 and CRn1 are set to 0000H < CRn1 < CRn0 ≤ ≤ ≤ ≤ FFFFH.
2. PPG output sets the pulse cycle to (CRn0 setup value + 1).
The duty ratio is (CRn1 setup value + 1)/(CRn0 setup value + 1).
Remark
n = 0, 1, 7 to 12
274
CHAPTER 8
TIMER/COUNTER FUNCTION
TMCn3
0
0
1
0
0
0
OSPEn
TOCn4
LVSn
0
1
0/1
User's Manual U15109EJ3V0UD
TMCn2
TMCn1
OVFn
1
0
0
CRCn2
CRCn1
CRCn0
×
0
0
LVRn
TOCn1
TOEn
0/1
1
1
Clears and starts on
match between TMn
and CRn0.
× : don't care
CRn0 as compare
register
CRn1 as compare
register
Enables TOn output.
Inverts output on match
between TMn and
CRn0.
Specifies initial value of
TOn output F/F.
Inverts output on match
between TMn and
CRn1.
Disables one-shot pulse
output.

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